Arti Chauhan

Software Engineer

Bengaluru, Karnataka, India12 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

14 years of expertise in ASIC Physical Design.
Specializes in timing closure and ECO debugging.
Proven track record in physical design flow optimization.

Stackforce AI infers this person is a specialist in ASIC Physical Design within the semiconductor industry.

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Skills

Other Skills

EngineeringVLSISoCEmbedded SystemsXilinxModelSimEDACMOSAnalog Circuit DesignPhysical VerificationTCLCircuit DesignFPGADigital ElectronicsMicroelectronics

About

With over 14 years of expertise in ASIC Physical Design, I have successfully taped out high-performance, low-power designs across mobile, networking, cloud, IoT, and digital TV applications. My experience spans floor planning, placement, clock tree synthesis, and routing, driving optimized timing closure, PPA, and physical verification across advanced nodes (45nm to 3nm, including Intel 16, 3 & 18A). I specialize in debugging complex design challenges, questioning flows & methodologies, and driving innovative automation for better convergence. My bird’s eye view of the PD flow ensures first-pass success, reducing iterations and accelerating design completion. Key Expertise: ✅ Timing Closure & ECO Debugging (Tweaker, PrimeClosure) ✅ Physical Design Flow Optimization (ICC2, FC, Innovus) ✅ Power, Performance, and Area (PPA) Trade-offs ✅ Cross-Domain Debugging (RTL to Sign-off) ✅ IR Drop & EM Analysis (RedHawk) ✅ Physical Verification (Calibre, ICV, PERC, DRC, LVS) ✅ Advanced Node Design (45nm → 3nm, Intel 16/3/18A) ✅ Scripting & Automation for PD Efficiency

Experience

12 yrs 7 mos

Total Experience

1 yr 9 mos

Average Tenure

6 yrs

Current Experience

Synopsys inc

4 roles

R&D Engineering, Sr staff Engineer

Promoted

May 2024 – Present · 2 yrs

Mgr II , Applications Engineering

Mar 2023 – Present · 3 yrs 2 mos

Applications Engineer, Staff

Dec 2021 – May 2023 · 1 yr 5 mos

Applications Engineer, Sr II

May 2020 – Dec 2021 · 1 yr 7 mos

Inphi corporation

Sr. Lead Engineer (ASIC Physical Design)

Mar 2019 – May 2020 · 1 yr 2 mos

Mediatek

Sr. Design Engineer

Mar 2015 – Feb 2019 · 3 yrs 11 mos · Singapore

Qualcomm

Engineer

Feb 2012 – Mar 2015 · 3 yrs 1 mo

Physical Designing

St-ericsson

Consultant Design engineer with Sasken Communication Technologies Ltd

Jul 2010 – Feb 2012 · 1 yr 7 mos · Noida, Uttar Pradesh, India

Worked with STE Noida as a Consultant ASIC physical designer.
My work involved floor planing , placement, clock tree synthesis, routing until sign off (signoff includes PV, PV includes DRC cleaning , fixing ERC/PM/ANTENNA/LVS/PERC, Timing Closure, Static/Dynamic IR drop analysis & fixes) for low power , high frequency systems & subsystems

Csir-ceeri

Project Associate

Mar 2009 – Jun 2010 · 1 yr 3 mos · Pilani Rajasthan, India

IC Fabrication.(MEMS)

Tiit

Physical Design trainee

Jul 2008 – Jan 2009 · 6 mos

I worked on Cadence suit for ASIC physical designing.

Evalueserve

Research Associate

Feb 2008 – Jun 2008 · 4 mos

Worked on Patent drafting, Freedom to operate (FTO) search, Validity Search, Novelty Search and Prior Art Search, worked for ‘Qimonda’, which is a world’s leading creative semiconductor memory development company,also handled projects like bucketing of different patents based on semiconductor technology , Validity, Novelty and prior art search for ‘Quimonda’. I drafted provisional patent application for Wisdom tap, which is a Hi-tech Company in Bangalore, Handled Freedom to operate search for a MEMS product for a US Client.

Amity university

University Lecturer, Electronics & Communication engineering

Jul 2007 – Feb 2008 · 7 mos

Subjects taught: Digital Electronics; Microprocessor 8086 theory and Lab; VLSI Design; Microelectronics.

Mody university

Lecturer and Course coordinator (VLSI Systems and subsystems)

Aug 2006 – Jun 2007 · 10 mos

Subjects taught: Digital Electronics; Microprocessor 8086 (theory and Lab); VLSI Systems and Subsystems; VHDL (theory and Lab) and handled other responsibilities