KISHORE BALA — Product Engineer

Dynamic,result oriented,innovative and passionate DFT Design professional with 16 years of Industrial Experience in DFT Design and ATE post silicon testing. DFT Resposibilities: • Scan architecture and scan insertion,• ATPG pattern generation and timing and No-timing simulation• ATPG timing and No-timing simulation debug • Atpg pattern translation• ATPG compression/X-tol techniques• MBIST implementation and Verification• BSCAN/JTAG Implementation and Verification• Low power DFT techniques• Effective silicon debug• Top Level RTL integration using Magillum tool DFT tools worked: • Fastscan,TestKompress,Tetramax,DFT Compiler,Cadence ET •Verdi,NCSim,VCS, Modelsim,QuestaSim ATE Test Resposibilities: Ø Project Feasibility Study Ø Test plan creation Ø schematic development using ORCAD and PADS software. Ø Load board Design and verification Ø Wafer and Package testing for Digital and Analog devices Ø Test program development for single site and multisite testing Ø Pattern Translation using VTRAN and TSSI tool. Ø Test (Scan and MBIST and functional) Pattern debugging Ø Test Method development for critical Digital and Analog tests. Ø Test program optimization for Test Time, Test Data Volume reduction. Ø Device DC/AC Characterization Ø PVT corner testing Ø Device screening Ø Test Program Release. ATE Tester Worked: • Verigy 93k SoC pinscale tester (both analog and Digital tests)

Stackforce AI infers this person is a DFT and ATE testing expert in the semiconductor industry.

Experience: 19 yrs 9 mos