Apr 2018 – Feb 2022 · 3 yrs 10 mos · Bengaluru Area, India

• Responsible for RTL to GDS of server SOC's ensuring STA and sign-off flows to adhere to the milestone and quality tape-in.
• Closely worked with multiple stakeholders to drive multiple domain challenges by collaborating with a great team and exhibiting diversified solutions.

Oct 2014 – Apr 2016 · 1 yr 6 mos · Bengaluru

• $ Good understanding of Physical Implementation of network and mobile IP's including floor-plan, Placement, CTS, Routing, STA, RV and sign-off checks using hierarchical design flow (bottom-up approach)
• $ Worked on a cutting edge project with RLS methodology for a micro-architecture sever chip from Synthesis to GDS-II sign-off
• $ Hands on experience in designing with layout design for memory and clock utility using Synopsys ICC in 14nm and 10nm feature size for reliability and DFY
• $ Estimation and Optimization. Owning complete responsibilities of Digital IP reviews pertaining to FV,CLP,PV & PDN domain
• $ Custom placement and routing for design specific requirement
• $ Implementing low power techniques for multi-stage domain design
• $ ECO (Engineering Change Order) implementation
• $ Timing sign-off and Physical Verification of chip
• $ LVS and DFM rule checks and validation for design
• Apart from above, taken up roles in training/helping Team members wherever needed, communication with Packaging/Board level Team & coordinating with cross-site teams to get Quality outcome.

Aug 2013 – Jul 2014 · 11 mos · Bengaluru Area, India

Apr 2016 – Apr 2018 · 2 yrs · Bengaluru Area, India

• Working for the advanced 7nm, 10nm, 14nm and 28nm technology nodes with intricate process and methodology to deal around Netlist to GDS sign-off
• The major responsibility is to build an efficient Synthesis mechanism for Clock macro taking forward with Floorplan, Placement, CTS, Routing, PV, Extraction, Timing analysis and sign-off
• Netlist to GDSII flow Implementation
• Worked on physical design implementation, physical verification and static timing analysis
• Worked on physical design flow Floor planning, Placement, Clock Tree Synthesis and Routing
• Participated in the block level RC Extraction and timing closure (STA)
• 10 nm Physical design implementation and optimization of blocks
• Responsible for the complete physical design flow from Netlist to GDSII which includes Floor Planning, Pin Placement, Placement, Clock Tree Synthesis, Routing
• Performing many iterations to reach timing closure in PT by interacting with front-end design/RTL designers
• Static Timing Analysis, Cross-talk Analysis, Parasitic Extraction, LEC, IR Drop Analysis and ECO for blocks
• Design Metrics: 14nm technology node with 14lpp SAMSUNG process, 10 metal layer design, Std cell utilization of ~60%, 16-18 macros, 4-5 million standard cells, multi clock design with dominant clock frequency of 650MHz, 1 max corner and 2 min corners.
• Responsible for carry out all the phases from Synthesis to Routing including Placement, Scan chain reordering, CTS, Post CTS incremental placement and Routing on my partition.
• Important tasks performed were synthesis, P&R, post route timing fixes and ECO.
• Optimized the design for the congestion and timing through these phases.

Jun 2012 – Dec 2012 · 6 mos · Bangalore Urban, Karnataka, India

Jan 2011 – May 2012 · 1 yr 4 mos · Bangalore Urban, Karnataka, India · On-site

• Worked on assembly code development for a Rexroth and Simens made PLC and download it for the desired functioning of the machine using Assembly and C language under the Technical Engineering Force (TEF) which comes under RBIN, Audugodi, Hosur road, Bangalore.
• The responsibility is for developing automotive tools along with CAN, FlexRay, UDS functionality.