rajeev singh

CEO

Bengaluru, Karnataka, India26 yrs 4 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Proven leader in digital design implementation.
  • Expert in low power design complexities.
  • Instrumental in defining digital design methodologies.
Stackforce AI infers this person is a Semiconductor Design Expert with extensive experience in ASIC and SoC development.

Contact

Skills

Core Skills

SocDigital Design ImplementationAsic DevelopmentDigital Design

Other Skills

Physical DesignRTL2GDSAI SoCWireless ConnectivityGraphics CoresCamera & Image SensorsASICNetworkingWirelessHome EntertainmentDDR PhyDigital CoresHigh Speed Serial LinksARMPowerPC

About

Rajeev currently with Samsung Semiconductor, Bangalore as Group Head, responsible for SoC Digital Implementation as RTL2GDS for various Samsung in-house product lines, like Samsung Exynos Mobile Volume and Exynos Automotive AI SoC, Graphics Cores, Wireless Connectivity, Camera & Image Sensor. Well aware of the low power design complexities & implementation requirements for the related product lines linked with Mobile including ARM CPU Cores, Gfx Cores, wide range of low power ASICs experience. Also has been responsible for large customer ASICs development, primarily Networking, Ethernet Switch. Rajeev is proven leader in field of digital design implementation, well known for seeding new teams plus developing required competencies. Across the years has been successful accomplishing the challenges, mentoring the young talent. Rajeev has been instrumental in appreciating the increase in SoC implementation complexity coupled with the technology challenges. Constantly keep finding new ways to accomplish more with less with improved quality. Rajeev successfully been able to define flows and methodologies in field of digital design to suit the design complexity.

Experience

26 yrs 4 mos
Total Experience
4 yrs 4 mos
Average Tenure
6 yrs 10 mos
Current Experience

Samsung electronics

Group Head, Director, Digital Implementation, Samsung Mobile and Image Sensor,

Jul 2019Present · 6 yrs 10 mos · Bengaluru, Karnataka, India

  • Rajeev presently driving the Digital Design Implementation for Samsung in-house products at SSIR, Bangalore. As a technology leader, responsible for RTL2GDS for product line ranging from Exynos products targeted for Mobile Volume Market, AI SoC for Automotive, Wireless Connectivity, Graphics Cores, Camera & Image Sensors projects.
Physical DesignSoCDigital Design Implementation

Mediatek

2 roles

Dy. Director

Promoted

Jul 2017Jun 2019 · 1 yr 11 mos · Bangalore

  • Worked with MediaTek Bangalore as Dy. Director within Design Technology, responsible for SoC development in various product lines like. networking, home entertainment and wireless product.
  • Also responsible for large customer ASICs development across the above product lines, primarily Networking.
Physical DesignSoCASIC Development

Sr. Dept. Manager

May 2014Jul 2017 · 3 yrs 2 mos · Bangalore

  • Responsible for developing Networking, ASICs and Home Entertainment chips across technology nodes, with latest in N7
Physical DesignASIC Development

Ibm india

Backend Design Manager

Jun 2011Mar 2014 · 2 yrs 9 mos · Bangalore

  • Developed High Speed Serial Links, Digital Cores, DDR Phy (DDR3, DDR4), Customer ASICs, IBM Server and TestChips across technology nodes, 45nm, 32nm, 14nm
Physical DesignDigital Design

Freescale semiconductor

Project Manager

Jun 2006Jun 2011 · 5 yrs

  • Developed Mobile CPUs, ARM core based, PowerPC Cores (e300), DSP core (P2002) for Wireless Team.
  • Developed the test-chips & product prototypes for qualifying any IP within digital, custom, analog domain. Creation of custom blocks for IP characterization on silicon.
Physical DesignDigital Design

Intel

2 roles

Synthesis and Placement Lead

Promoted

Mar 2003Jun 2006 · 3 yrs 3 mos

  • Delivered onto the four generations of Intel Mobile Chipset (MCH): rtl & collateral/IP management, methodology/flow enhancements, synthesis, placement, clocks, timing, equivalency checking, routing
Physical DesignDigital Design

ASIC design engineer

Feb 2001Mar 2003 · 2 yrs 1 mo

  • Worked with Intel Microelectronics Services Groups. Was responsible for developing ASIC for Intel internal & external customers.
Physical DesignASIC Development

Avant!

Application Engineer

Sep 1999Jan 2001 · 1 yr 4 mos

  • Worked as Application Engineer providing support for Avant! APR tools (presently Synopsys)
Physical Design

Education

Bangalore University

BE

Jan 1995Jan 1999

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