G

Gaurav Maheshwari

Director of Engineering

Bengaluru, Karnataka, India28 yrs 10 mos experience
Highly Stable

Key Highlights

  • 20+ years of ASIC/SoC lifecycle expertise
  • Led 20+ IC/SOC tape outs to mass production
  • Strong team management and leadership skills
Stackforce AI infers this person is a seasoned ASIC/SoC engineering manager with extensive experience in VLSI design and project management.

Contact

Skills

Core Skills

AsicSoc

Other Skills

Timing ClosureRTL to GDS ExecutionConstraint DevelopmentTeam ManagementAnalytical SkillsTroubleshooting SkillsSynthesisSTADFTASIC DevelopmentVLSIVerilogTCLPerlStatic Timing Analysis

About

Summary • Over 20+ years of experience • Strong expertise in all phases of ASIC/SoC life cycle • Self Motivated & Strong Team Player • Always Willing to Learn and mentor other team members • Excellent Leadership qualities demonstrated through First Time Right project execution. • Exposure in handling diversified and cross cultural team across Globe (US & Europe). • Strong Exposure to entire IC Design Process from Specification until Final mass production. • Excellent capabilities in team management. Self-driven, focused and detail oriented with strong analytical and troubleshooting skills. • Always looking for new Challenges & Flexible to adapt to any role as per the project requirements. • Core competencies in Synthesis and STA (Timing closure). • Worked on cutting edge 14nm, 22nm, 28nm, 45nm and 65nm technologies. • Involved in 20+ IC/SOC tape outs and seen multiple products until mass production. Specialties: VLSI ASIC Project Management Synthesis/STA (timing closure)

Experience

28 yrs 10 mos
Total Experience
7 yrs 10 mos
Average Tenure
5 yrs 4 mos
Current Experience

Intel corporation

Senior Engineering Manager

Jan 2021Present · 5 yrs 4 mos · Greater Bengaluru Area

Aricent (cap gemini)

Director-Technology

Oct 2017Jan 2021 · 3 yrs 3 mos · Bengaluru, Karnataka, India

  • Rich experience in timing closure in Multiple 100M+ gate ASIC/SoC. Experience in RTL to GDS execution.
  • Core competencies in Constraint Development in STA and Timing closure.
  • Excellent capabilities in team management. Self-driven, focused and detail oriented with strong analytical and troubleshooting skills.
Timing ClosureRTL to GDS ExecutionConstraint DevelopmentTeam ManagementAnalytical SkillsTroubleshooting Skills+2

Wipro

2 roles

Principal Architect

Promoted

Jun 2000Sep 2017 · 17 yrs 3 mos · Bangalore

  • Rich experience in timing closure in Multiple 100M+ gate ASIC/SoC. Experience in RTL to GDS execution.
  • Core competencies in Constraint Development in STA and Timing closure.
  • Proven strengths in mapping customer's needs and committing resources to achieve project accomplishment within defined timelines and cost.
  • Excellent capabilities in team management. Self-driven, focused and detail oriented with strong analytical and troubleshooting skills.
  • Team leader, trainer and a natural motivator with well organized work habits.
  • Good Communication skills.
Timing ClosureRTL to GDS ExecutionTeam ManagementAnalytical SkillsTroubleshooting SkillsASIC+1

Senior Consultant

Jun 2000May 2013 · 12 yrs 11 mos · Bangalore

  • Core competencies in Synthesis and STA (Timing closure).
  • Experienced in DFT area.
  • Experience in all fields of ASIC Development
  • Experience in design and development in multiple ASIC of over 150M gates ASIC
  • Worked as Senior Project Manager handling Tier-1 customer
SynthesisSTADFTASIC DevelopmentASIC

Cdot

Research Engg

Jan 1997Jan 2000 · 3 yrs

  • Currently known as CDOT Alcatel Research Centre. I worked for 3 years in CDOT and worked on WCDMA technology.

Education

Indian Institute of Technology (Banaras Hindu University), Varanasi

B TECH — Electronics & Communication

Jan 1993Jan 1997

Birla Institute of Technology and Science, Pilani

Master’s Degree — Micro Electronics

Jan 2013Jan 2014

Mahanagar Boys

Jan 1990Jan 1992

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