Vishnu Uppula

Software Engineer

Hyderabad, Telangana, India7 yrs 6 mos experience

Highly Stable

Key Highlights

7+ years of experience in physical design.
Expert in optimizing power, performance, and area metrics.
Proficient in RTL-to-GDS implementations.

Stackforce AI infers this person is a Semiconductor Design Engineer specializing in advanced SoC technologies.

Contact

Skills

Core Skills

Silicon DesignSign-off Quality Data GenerationPhysical Design ProcessLow Power Soc Design

Other Skills

Collaborative Problem SolvingSemiconductor EngineeringMindMeisterPower OptimizationOptimization TechniquesOptimizationAnalytical SkillsOral CommunicationScriptingDesign ToolsProblem SolvingCommunicationElectrical EngineeringHardware DevelopmentCircuit

About

As a Lead Design Engineer at Cadence with over 7+ years of experience in physical design, I specialize in optimizing power, performance, and area metrics for advanced System-on-Chip (SoC) technologies. My work is dedicated to generating high-quality sign-off databases while addressing critical design challenges such as timing, congestion, and power optimization. Throughout my career, I have focused on delivering seamless RTL-to-GDS implementations and ensuring industry-leading silicon designs. By leveraging my expertise in MindMeister, power optimization, and advanced optimization techniques, I strive to contribute to innovative and efficient semiconductor solutions.

Experience

7 yrs 6 mos

Total Experience

6 yrs 2 mos

Average Tenure

1 yr 4 mos

Current Experience

Cadence

Lead Design Engineer

Jan 2025 – Present · 1 yr 4 mos · Hyderabad, Telangana, India · On-site

Amd

3 roles

Sr. Silicon Design Engineer

Promoted

Oct 2022 – Dec 2024 · 2 yrs 2 mos

Working as a sub-lead handling 6 blocks out of which hands-on two blocks in GFX IP and my primary responsibility is to generate sign-off quality data base by considering all design metrics’s

Collaborative Problem SolvingSemiconductor EngineeringSilicon DesignSign-off Quality Data Generation

Silicon design engineer 2

Aug 2019 – Oct 2022 · 3 yrs 2 mos

In brief, my primary responsibility is the physical design process involving the transformation of RTL level netlist description to foundry specified GDS2 description involving steps like Synthesis, Floor planning , Placement, Clock tree synthesis,Routing,Static timing analysis,Physical verification (DRC, LVS)for realizing next generation low power AMD APU SOCs

Collaborative Problem SolvingSemiconductor EngineeringPhysical Design ProcessLow Power SoC Design