Feb 2021 – Jun 2022 · 1 yr 4 mos · Bengaluru, Karnataka, India

• ▪ Drove methodology development and implementation for identifying security validation requirements from threat model. As a result of
• this, more than 20 gaps were identified on the pilot project, and validation suite was enhanced to plug those.
• ▪ Developed portion of automated flow for evaluating SDL compliance of projects.
• ▪ Engineered a new software exploit for Buffer Overflow Vulnerabilities, accepted for publication and demo in RSA Conference 2022.
• ▪ Participated in a server product hackathon and identified security gaps having impact beyond server products.
• ▪ Architected Threat Model of Debug features of a server platform, identifying 7 new threats.
• ▪ Developed new automated flow for uncovering use-after-free vulnerabilities, overcoming the shortcomings of existing methods.
• ▪ Served as a reviewer for the security track of WE Local India 2022 Conference.

Jul 2020 – Feb 2021 · 7 mos

• ▪ Drove and was responsible for Quality of SoC Security Verification for the projects with maximum reuse.
• ▪ Represented SoC Security Verification to the Management, and related responsibilities by providing inputs and making decisions by
• considering both technical aspects and project milestones driven from customer needs.
• ▪ Worked in close collaboration with Security Architects for defining SoC Security Architecture of Automotive SoCs
• ▪ Point of Contact for security architecture decisions on previous devices and their motivation. Provided inputs to IP design, Frontend
• Integration and Security Architecture teams.
• ▪ Drove closure of security architecture decisions by providing design and architecture solutions which are acceptable by all domains. Also
• ensuring alignment among projects to enable reuse at different design development platforms.
• ▪ Found new security vulnerability scenarios, with improved understanding of attacks, affecting multiple devices for the new and previous
• architectures.

Mar 2018 – Jun 2020 · 2 yrs 3 mos

• ▪ Lead SoC Verification sign-off for Common Security Subsystem of 4 SoCs.
• ▪ Worked in close collaboration with Security Architects for defining SoC Security Architecture of Automotive SoCs
• ▪ Part of security architecture discussions and provided inputs related to learnings from vulnerability issues identified in previous devices.
• The inputs were considered and relevant changes in the security architecture were made during the architecture definition itself,
• improving the effective cost of such issues.
• ▪ Drove alignments and handoffs with other teams at SoC platform to implement and verify security features, like DFT, Safety, Debug etc.
• ▪ Found numerous vulnerability scenarios in the newly developed much more complex security architecture for next-gen devices. The
• required fixes significantly changed the security architecture, actively participated in these decisions and architectural updates.

Feb 2016 – Apr 2018 · 2 yrs 2 mos

• Ownership of verification of all Security modules for on-chip Flash protection.
• ▪ Verification of Secure boot, Secured access of debugger to on-chip resources and test access
• ▪ Developed automated flow to run secure boot with all other tests for Cross-coverage.
• ▪ Identified multiple corner case scenarios for security breach.
• ▪ Created TAG based reference document based on learnings from identified scenarios for enhancing security verification in all projects,
• which was made part Tape out check-list.

Jun 2013 – Feb 2016 · 2 yrs 8 mos

• Responsible for SoC verification of on-chip flash protection security IPs. Started the concept of finding vulnerability issues as part of
• security verification.
• Responsible for SoC verification of the Debug subsystem of Cortex –A53 core and CRC IP. Created automation for functional
• improvements finding new defects. Also, verified SoC IOMUX structure using Formal.