Shirish Kulkarni

Software Engineer

Hyderabad, Telangana, India19 yrs 8 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 13 years of experience in VLSI design and verification.
  • Completed 12 tapeouts as a physical verification engineer.
  • Expert in managing physical design and verification flows.
Stackforce AI infers this person is a Semiconductor Design Engineer with extensive experience in physical design and verification.

Contact

LinkedIn

Skills

Other Skills

Physical VerificationPhysical DesignEmbedded SystemsLVSDRCVLSIASICDebuggingFPGAEDAStatic Timing AnalysisVerilogCMOSSoCTCL

About

13 years of experience in VLSI. Worked as block level physical design implementation engineer with Wipro Technologies for 2 years. As physical verification engineer with LSI India R & D Pvt. Ltd for past 5 years and have completed 12 tapeouts. As physical verification engineer with Smartplay Technologies. Worked as PnR and PV engineer at Mediatek for block and full chip. Worked with Graphene Semiconductor Services Private Limited for U.S. based clients.

Experience

19 yrs 8 mos
Total Experience
2 yrs 5 mos
Average Tenure
4 yrs 3 mos
Current Experience

Ampere

Principal Engineer

Feb 2022 – Present · 4 yrs 3 mos · Pune

Amd

SMTS Engineer

Dec 2019 – Jan 2022 · 2 yrs 1 mo · Greater Hyderabad Area

Hcl technologies

Technical Manager

Sep 2018 – Nov 2019 · 1 yr 2 mos · Pune Division, Maharashtra, India

  • Physical Design and custom routes for flat chip

Graphene semiconductor services pvt ltd.

Lead Techincal Staff

Feb 2017 – Sep 2018 · 1 yr 7 mos · Pune Division, Maharashtra, India

  • Physical Design Implementation of Blocks.

Mediatek usa inc.

Lead Engineer

Jul 2014 – Jan 2017 · 2 yrs 6 mos · Bangalore

  • Physical Design Implementation for blocks

Smartplay technologies

Lead Engineer

Sep 2013 – Jul 2014 · 10 mos · Bengaluru, Karnataka, India

  • Mange the complete PV flow.
  • PnR flow setup for block.

Lsi corporation

Senior Project Engineer

Sep 2008 – Sep 2013 · 5 yrs · Pune

  • Resposnsible for all physcial verification checks (DRC, LVS, DFMLCC, ESD).
  • Implementation of power grid and custom routes.
  • IR drop analysis using cooltime.

Wipro technologies

Project Engineer

Jun 2006 – Sep 2008 · 2 yrs 3 mos · Pune

  • Complete PnR flow for block.

Education

University of Mumbai

Master of Science (M.Sc.) — Physics(Electronics) - Microprocessors and Microcontrollers

Jan 2001 – Jan 2003

C.H.M. College

Bachelor of Science (B.Sc.) — Physics

Jan 1999 – Jan 2001

Inner Wheel School

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