Apr 2020 – Aug 2024 · 4 yrs 4 mos · Bengaluru Area, India

• Leading the Pre-Si Validation Activity for Data Center, HPC , Desktop, Performance Notebook Segment Products . Role includes Emulation Validation , Performance Validation, Power Estimation, SW Usecase and Post-Si Usecase Validation

Jul 2017 – Mar 2020 · 2 yrs 8 mos · Bengaluru Area, India

• Leading the Emulation Validation activity for the intel next generation Client, Notebook, IOTG segment Products. Role includes Emulation Model Enabling, Interface bringup, Content Validation, Perf/Stress Content Enabling for Multimedia IPs, Post-Si Enabling

Apr 2017 – Jul 2017 · 3 mos

Nov 2014 – Mar 2017 · 2 yrs 4 mos

May 2014 – Nov 2014 · 6 mos

• Virtual Platform Development for Intel Mobile platform
• IP Development and Verification .

Apr 2013 – May 2014 · 1 yr 1 mo

• Role IP Development and Verification (SystemC, TLM2.0)
• SystemC and TLM2.0 Modelling and Verification Activities (Test case identification, Testbench development, Coverage driven verification), cmake and gmake build environment development and test bench automation
• Integration of the IPs and platform build verification
• Specification extraction and SystemC Model Development
• Development of the Testbench environment and Testcases
• SystemC Platform creation using Synopsys tools PCT and coMET.
• Testcase running using Virtualizer VPA, METeor and debugging using Trace32.
• Modelling and Verification of ARM ISS and modules System Timer, RTC, Interrupt Controller, Clock Generation, Power Management unit, Power controller unit etc..

Aug 2011 – Apr 2013 · 1 yr 8 mos · Bangalore

• Technical Presentation, support, Evaluation, Deployment, integration for Verdi (Springsoft), Siloti (Springsoft), DVT eclipse Smart Editor for System Verilog and E language (AMIQ)
• Tool Training for Verdi (SystemVerilog Testbench, SystemVerilog Assertion, Low Power Debug, nWave, nTrace, nSchema, TFV, nECO, nCompare, nAnalyzer, nMemory), Siloti, DVT eclipse (AMIQ)
• Theoretical and Practical exposure on frontend as well as on backend design flow
• Development of Perl/Tcl Script to add automation in Frontend Design flow
• Providing effective EDA solutions to the clients.
• Handling Pre sales and Post sales activities for Verdi, Siloti, DVT eclipse in Bangalore, Hydrabad, Pune, Delhi location.

Jun 2010 – Apr 2011 · 10 mos

• TLM based verification environment
• Working experience in multiple language verification domain.( C, VHDL, verilog, SystemC )
• Error debugging of complex structure of cable modem IP.
• GDB debugger, Functional and Code coverage.
• Developed checker in Perl script.
• Development of BFM.