Jan 2019 – Sep 2019 · 8 mos · Bangalore Urban, Karnataka, India

May 2017 – Dec 2018 · 1 yr 7 mos · Mumbai, Maharashtra, India

Jun 2016 – May 2017 · 11 mos · BANGALORE, KARNATAKA, INDIA

Apr 2013 – Oct 2015 · 2 yrs 6 mos

• project coordinator,
• subjects handled :- STLD/DLD,VLSI

Apr 2013 – Oct 2015 · 2 yrs 6 mos

• Design & FPGA Implementation Of VGA Controller; The aim of the project is to design and implement VGA Controller which can generate the Control Signals according to standard VGA timings to print Horizontal, Vertical 8 colour spectrum on monitor screen of 640x480 pixels. Project verification is using verilog.
• Software Tools: Xilinx ISE, ModelSim Simulator
• Hardware: Spartan 3E FPGA starter kit.
• 2. DESIGN OF PIPELINED AND PARALLEL FFT PROCESSOR USING RADIX-4 AND FPGA
• Description Talking about the main thing which you can say the backbone of this project is the “Design Of Pipelined FFT Processor Using FPGA ”. In this proposed work we are going to develop FFT processor for different wireless communication systems by introducing pipelined and parallel method in the butterfly unit of the processor and implementing the FFT algorithm with radix-4 butterfly algorithm in the processor.
• Software Tools: Xilinx (XPS)