Revathi S

Product Manager

Bengaluru, Karnataka, India22 yrs 8 mos experience

Highly StableAI ML Practitioner

Key Highlights

Expert in EDA with extensive verification experience.
Strong background in machine learning for automation.
Proven leadership in project management and team development.

Stackforce AI infers this person is a highly skilled EDA engineer with strong expertise in verification and automation.

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Skills

Core Skills

Machine LearningSystemverilogProject ManagementVerification And Validation (v&v)Core JavaC++JavaTeaching

Other Skills

Python (Programming Language)Cursor AIGHCPCJavaScriptPerlTeam ManagementHTMLXMLCollaborative R&DTrainingEDAMultithreadingLogic SynthesisIPXACT

Experience

22 yrs 8 mos

Total Experience

5 yrs 8 mos

Average Tenure

Current Experience

Synopsys inc

5 roles

Senior Staff R&D Engineer

Feb 2024 – Jan 2026 · 1 yr 11 mos

Business Group: Technology and Product Group
Role: Individual Contributor
Coverage and Verification plan development for CXL, PCIE, UCIE, NVME
Adoption of Machine Learning tools for VIP development Automation.
Applying Release automation to products in VIP portfolio.

SystemVerilogMachine LearningPython (Programming Language)Cursor AIGHCP

Staff R&D Engineer

Nov 2021 – Feb 2024 · 2 yrs 3 mos

Business Group: Systems Design Group
Role: Lead developer and Project Manager
Coverage development for CXL VIP.
Development of Automation utility for Coverage, Protocol Check and Verification Plan creation.
Deployment of automation utility in Coverage, Protocol check, and Test Verification plan development for VIP products like PCIE, CXL, UCIE, NVME, Ethernet, DDR, LPDDR and Display protocols.
Enhancement in Class reference generation to support Root cause Analysis for Debugging.
Develop Release Automation utility for Verification IP products.

Project ManagementSystemVerilogCC++Python (Programming Language)

Senior R&D Engineer II

Jun 2018 – Oct 2021 · 3 yrs 4 mos

Business Group: Systems Design Group
Role: Lead developer and Manager
Coverage development for CCIX VIP.
Enhancement of tool for Class reference generation for Verification IPs: Memory, Storage, AMBA, Bus interfaces, Ethernet, PCIE, USB, MIPI, Automotive and Sub systems that involve multiple protocols.
Creation of NLP based search framework for Verification IP class references.
Maintenance of tools for build, release, and licensing of Verification IP products.

Project ManagementSystemVerilogCC++Python (Programming Language)JavaScript+2

Senior R&D Engineer I

Promoted

Jun 2013 – May 2018 · 4 yrs 11 mos

Business Group: Verification Group
Role: Lead developer and Supervisor
Validation of PCIE Verification IP.
Configuration of PCIE Verification IP config space as per DUT RAL model.
Setting up flow for creation of functional coverage, protocol check coverage and test plan for achieving Verification closure and linking with protocol specification.
Upgradation of parser of Class reference generating tool for Verification IP to classify class reference content as per Verification context.
Addition of filters in class reference content for improved information retrieval.
Enhanced report generation – csv and pdf file formats
Setting up failure reporting mechanism in daily regression.

Verification and Validation (V&V)SystemVerilogProject ManagementCC++JavaScript+3

R&D Engineer

May 2008 – May 2013 · 5 yrs

Business Group: Solutions Group
Role: Lead Developer
Developed Protocol Analyzer tool for debugging Memory Verification IPs.
Netlist generation for formal verification.
Constraints translation in Synthesis flow.
Hardware / Software integration.
Log enhancements in Synthesis flow.

Core JavaCC++

Synplicity

Software Engineer

Aug 2007 – May 2008 · 9 mos

Worked in Embedded group and was involved in developing a tool for the assembly of processor based systems/platforms as per IPXact standard and wrapper netlist generation.

JavaCollaborative R&D

Intel

Intern

Mar 2007 – Jul 2007 · 4 mos

Work area:
In core engine part of a micro architecture model based functional test generation tool .
> Development of a reference model:
Implemented a reference model to create cache models for multi processor, multi core and multi threaded environment.
> Creation of Event Library Generator:
Implemented a module that will create the various transactions of events automatically and store in a library.

Velammal engineering college

Teaching Faculty

Jun 2001 – Aug 2005 · 4 yrs 2 mos

Work Profile:
> Teaching subjects in Computer Science & Engineering and Electrical & Electronics Engineering that include Data Structures, Analysis of Algorithms, Programming languages, Operating Systems, Software Engineering, Computer Networks, Network Security and network management protocols, Microprocessors, Circuit theory.
> Written three quick reference books on
1. Computer Networks
2. Network Protocols, Management and Security
3. Software Engineering
> Project coordinator for final year under graduate projects.
> Coordinator for conducting national level project exhibitions/competitions and technical symposiums.
> Coordinator for scheduling classes and conducting theory and practical examinations.

TeachingProject ManagementTraining