Rajesh Chopra

CEO

Bengaluru, Karnataka, India21 yrs 9 mos experience
Highly Stable

Key Highlights

  • 24 years of SoC/ASIC design experience.
  • Expert in managing complex SoC projects.
  • Strong collaboration with cross-functional teams.
Stackforce AI infers this person is a Semiconductor Design Expert with extensive experience in SoC and ASIC development.

Contact

Skills

Other Skills

VerilogRTL designVLSIDFTVHDLFormal VerificationIntegrationMixed SignalLow-power DesignIntegrated Circuit DesignEDASet Top BoxFPGADebuggingSemiconductors

About

24 yrs of SoC/ASIC Design experience of varied roles in technical and leadership areas. Working for high performing and low power SoC from Specs to GDSII (catering to wide range of applications). From Last 2 years, i am working as HW ASIC SoC Silicon Project manager - Including requirements capture, feasibility study, planning, resource task allocation, risk analysis, cost analysis, co-ordinating, executing, delivering complex SoC projects in 40nm/28nm techno. I've also had a strong program facing role, supporting and collaborating with Marketing, System Architecture, Software, Validation, Engineering, Package and Boards design. Specialties: SoC Design and Development for Complex/High performance Set-top-Box for Cable, Satellite and Terrestrial markets. SoC Silicon Project Manager. SoC Design Lead. SoC Design and integration. SoC Micro-Architecture. IP & Sub-System Design SoC Interconnect Design

Experience

21 yrs 9 mos
Total Experience
9 yrs 1 mo
Average Tenure
3 yrs 7 mos
Current Experience

Rivos inc.

Principal Member of Technical Staff

Oct 2022Present · 3 yrs 7 mos

Intel corporation

SoC design FE Lead/Manager

Aug 2015Sep 2022 · 7 yrs 1 mo · India

  • Logic Lead

Stmicroelectronics

3 roles

Sr. Staff Engineer

Promoted

May 2012Aug 2015 · 3 yrs 3 mos

  • SoC Silicon Project Manager, STB SoC Micro-Architecture

Technical Specialist

Promoted

Aug 2008Apr 2012 · 3 yrs 8 mos

  • SoC Design Lead, SoC Design and Integration, Interconnect Design

Sr design Engineer

May 2004Jul 2008 · 4 yrs 2 mos

  • IP Design, Sub-System Integration.

Education

Kurukshetra University

Master of Technology (MTech) — Electronics

Jan 2000Jan 2002

Kurukshetra University

M.Sc — Electronics

Jan 1997Jan 1999

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