Shashank Kumar

Product Engineer

New Delhi, Delhi, India3 yrs experience

Key Highlights

Expert in Power Integrity and ASIC Design.
Strong automation skills with Python.
Passionate about VLSI and embedded systems.

Stackforce AI infers this person is a VLSI and Embedded Systems Engineer with strong software development skills.

Contact

kumarshashank822@gmail.com LinkedIn

Skills

Core Skills

Power IntegrityAsic DesignWeb Development

Other Skills

EMIR AnalysisSignoff ActivitiesIR BudgetDeep Power Integrity analysisAutomation FlowsPython AutomationRedhawk-scCadence InnovusCadence CalibreSynopsys ICVMySQLJavaScriptReact.jsHTML5CSS

About

" Success Comes to those who are hardworking enough to get it..." Over The past few years I have been learning so many things without any desire to get well paid but with a desire to become well knowledgeable. Here Introducing myself - I am Shashank, a passionate technocrat, pursuing Masters in VLSI from Netaji Subhas University of Technology. # Physical Design (Power Integrity) Engineer at STMicroelectronics, the Second largest semiconductor manufacturing Multinational Company in the world. # I have a great passion in VLSI Design skilled in ASIC Design, verilog, system verilog, UVM, C++, Python, Linux. # Worked on various tools like Ansys Redhawk-sc, Cadence Virtuoso, Xilinx, LT spice and Electric. #Leveraged skill set in both front-end and backend design of VLSI. # Throughout my Academic and professional journey, I have learnt many things diversely in software as well as hardware domains, well versed with both of them. # I am a QUICK Learner, that is one of my biggest strength. # Contact at - shashank.pg23@nsut.ac.in

Experience

3 yrs

Total Experience

10 mos

Average Tenure

11 mos

Current Experience

Stmicroelectronics

2 roles

Physical Design PDN Engineer

Jul 2025 – Present · 11 mos · Hybrid

=> Handles EMIR Analysis and Signoff Activities for the SOC based on various technodes ranging from 40nm to 5nm.
=> Resolves Critical EMIR issues on Grid to stay within IR Budget and align with optimal use of area and high performance with low IR drop.
=> Does Deep Power Integrity analysis at each stage during RTL to GDS implementation. Give suggestions for better IR results across SOC.
=> Responsible for EMIR Flow development across various Projects
=> Have extensive experience and expertise on Redhawk-sc for EMIR Analysis
=> Responsible for Creating various Automation Flows for time saving and increased efficiency for numerous IR activities.
=> Experienced with Working and IR analysis of both Flip Chip and Wirebond SOCs.
=> Possess great problem solving skills advanced debugging.
=> Methodology Enhancement and Development.
=> Cross team Collaboration with various team for the successful implementation and tapeout of SOCs.
=> Specialized in Python Automation
Tools used : For IR Related activities - Redhawk-sc, Ansys current mode analyzer (CMA) For PV related activities - Cadence Innovus, Cadence Calibre, Synopsys ICV

EMIR AnalysisSignoff ActivitiesPower IntegrityIR BudgetDeep Power Integrity analysisAutomation Flows+6

Physical Design PDN Intern

Jul 2024 – Jun 2025 · 11 mos · Hybrid

=> Involved in EMIR Analysis and Signoff Activities for the SOC based on various technodes ranging from 40nm to 5nm.
=> Responsible for EMIR Flow development across various Projects
=> Have extensive experience and expertise on Redhawk-sc for EMIR Analysis
=> Responsible for Creating various Automation Flows for time saving and increased efficiency for numerous IR activities.
=> Experienced with Working and IR analysis of both Flip Chip and Wirebond SOCs.
=> Possess great problem solving skills advanced debugging.
=> Methodology Enhancement and Development.
=> Cross team Collaboration with various team for the successful implementation and tapeout of SOCs.
=> Specialized in Python Automation
Tools used : For IR Related activities - Redhawk-sc, Ansys current mode analyzer (CMA) For PV related activities - Cadence Innovus, Cadence Calibre, Synopsys ICV