Abhijit Joshi

Software Engineer

Bengaluru, Karnataka, India13 yrs 8 mos experience

Highly Stable

Key Highlights

Expert in CPU RTL design and microarchitecture.
Hands-on experience with Verilog/SystemVerilog and advanced pipelining.
Strong educational background from IIT Bombay.

Stackforce AI infers this person is a highly skilled CPU design engineer specializing in low-power, high-performance silicon architecture.

Contact

Skills

Other Skills

MatlabCVLSISystem on a Chip (SoC)PythonpandasUnixC++Microsoft OfficeLow-power DesignptpxCPU designRTL DesignLogic SynthesisVerdi

About

Driven by a passion for building future compute. I am a CPU RTL Design Engineer specializing in high-performance, power-efficient microarchitecture. From architecting pipelined RISC-V cores to optimizing custom ALUs and memory subsystems, I thrive at the intersection of digital logic, innovation, and silicon realization. With hands-on expertise in Verilog/SystemVerilog, FSM design, and advanced pipelining, I have contributed to RTL IPs for CPUs, AXI interfaces, and cache hierarchies. My workflow spans the full silicon lifecycle-from microarchitecture definition and RTL coding to synthesis, timing closure, and seamless handoff to physical design teams Strong engineering professional with a Master of Technology (M.Tech.) focused in Electrical Engineering from Indian Institute of Technology, Bombay.

Experience

13 yrs 8 mos

Total Experience

2 yrs 10 mos

Average Tenure

2 yrs 4 mos

Current Experience

Nvidia

Senior CPU Design Engineer

Jan 2024 – Present · 2 yrs 4 mos · Bengaluru, Karnataka, India · Hybrid

Sifive

CPU RTL Design

Jun 2022 – Jan 2024 · 1 yr 7 mos · Bengaluru, Karnataka, India

Google

Hardware Engineer

May 2019 – Jun 2022 · 3 yrs 1 mo · Bangalore

Intel corporation

SoC Design Engineer (SoC Power and Performance Lead)

Dec 2017 – May 2019 · 1 yr 5 mos · Bengaluru, Karnataka, India

Power and Performance modelling for Intel SoCs. Interfacing with the architecture teams to define usecase power envelope for different product segment. Also incharge of low power feature analysis and improvements for SoC

Qualcomm

3 roles

Sr. Lead Engineer (CPU design lead)

Jun 2017 – Nov 2017 · 5 mos

RTL design lead for ARM based CPU design. Integrating state of the art ARM CPU into the Qualcomm SOC designs. Power management and wrapper design for CPU. Responsible of sign off from RTL to validation to STA.

Sr. Design Engineer (CPU Low Power Lead)

Promoted

Nov 2014 – May 2017 · 2 yrs 6 mos

CPU Power Lead:
ARM based CPU Low Power Design and Sign-off Lead, Working on state-of-the-art ARM CPUs - Ananke/Artemis/A53, Power reduction strategies for back end implementation (Synthesis, Floor-plan, Placement, Routing), Library Cell Selection for low power, Worked on 10nm/14nm/28nm technology nodes, Low Power Clock Tree Design, Clock gating efficiency checks, CPU power modelling and Post Silicon Power Correlation across different Platforms, Basic synthesis using Synopsys DC and Cadence RC, Basic RTL Integration, Involved in Gate Level Simulations (GLS) for Dynamic power estimation and optimization, Successfully implemented dynamic and leakage power reduction techniques on taped out projects in 28nm/14nm, Provide power inputs for PDN design, Static and Dynamic IR drop analysis using Apache Red-Hawk, CPF and UPF definitions for Structural and Simulation checks, UPF based Power Aware Synthesis and Implementation.
SoC Die Power Lead:
SoC top level power estimation using Primetime-PX, Idle/Sleep power optimizations and target definitions, End-to-end Use case definition for SoC using Xactor based master for B/W generation and simulations (used to build Chip Power Model), Dynamic and leakage power estimation and correlation, Power Supply Buck Sizing, SoC Power partitioning and Power gating strategies for optimization, Co-ordination across cross functional teams from Front end, back end to Post Silicon and Software teams.

Design Engineer (SoC Low Power)

Jul 2012 – Nov 2014 · 2 yrs 4 mos

SoC Structural Low Power design and Checks using Conformal Low Power, Logic Equivalence Checks using Conformal LEC, Leakage and Dynamic Power estimation with Primetime-PX, RTL Power Estimation and optimization using Apache Power artist, SoC level Power estimation test bench definition using Xactor based approach