V

Vishwa Prabhat

Software Engineer

Bengaluru, Karnataka, India11 yrs experience
Highly StableAI Enabled

Key Highlights

  • 8+ years of semiconductor design experience
  • Expert in AI/ML flow deployment and PnR leadership
  • Proven track record of successful tapeouts
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in AI/ML and physical design.

Contact

Skills

Core Skills

Artificial Intelligence (ai)Physical DesignProject ManagementTool DevelopmentCustomer SupportTool EnhancementDebuggingDigital DesignBackend Asic Design

Other Skills

Optimization TechniquesScriptingCadence CerebrusCC++MatlabProgrammingVLSI

About

Semiconductor professional with 8+ years of experience across multiple roles varying from design engineer to application engineer at multiple organizations. Proven expertise in AI/ML flow deployment, PnR leadership, and tool enhancement, resulting in multiple tapeouts and customer satisfaction. Skilled in physical design, RTL-to-GDS implementation, and resolving complex technical challenges. Expertise in solving/debugging EDA problems, with effective collaboration, and commitment to excellence in semiconductor design. Strong communicator and collaborative team member, driving innovation and achieving targeted results for the organization in the specified timeline.

Experience

11 yrs
Total Experience
2 yrs 4 mos
Average Tenure
1 yr 8 mos
Current Experience

Mediatek

Senior Staff Engineer

Sep 2024Present · 1 yr 8 mos · On-site

Cadence design systems

3 roles

Principal Application Engineer

Jul 2024Sep 2024 · 2 mos

Lead Application Engineer

Promoted

Aug 2021Jun 2024 · 2 yrs 10 mos

  • AI/ML Flow Deployment: Successfully deployed Cadence AI/ML Flow (Cerebrus) in multiple customer Business Units (BUs), resulting in a recognition in 2023 DSG Q2-Q3 Worldwide Newsletter.
  • The Cerebrus work done also led to a Cadence LIVE Paper and subsequent blog, showcasing potential
  • testimonials for other customers.
  • Also, implemented multiple Cerebrus Apps to enhance PPA across multiple designs, achieving a 5% reduction in floorplan physical area for one design with no degradation in power and performance.
  • PnR Lead: Leading a PnR team to address critical customer issues, alongside delivering successfully multiple strategic initiatives like Cerebrus Flow, Smart Hierarchical Flow, and Joules X-replay leading to 12+ successive
  • tapeouts in 2023.
  • CAT Regression Flow Setup: Migrated customer's custom PnR flow to Cadence Stylus Flow, facilitating
  • regression runs for multiple blocks, enhancing tool version predictability. Also enabled onsite regression runs, aiding customer migration to latest tool versions which enabled them to adopt new tool features.
  • Knowledge Sharing: Conducted training sessions on Innovus PnR flow for customer new hires. Internally,
  • organized knowledge sharing sessions within and across the teams on Cerebrus AI/ML flow and Joules XReplay.
Artificial Intelligence (AI)Optimization TechniquesPhysical Design

Senior Application Engineer

Jan 2019Jul 2021 · 2 yrs 6 mos

  • Quality Execution and Customer Support: Ensured high-quality execution of strategic initiatives in PnR,
  • addressing customer issues/concerns promptly and providing proactive support.
  • Tool Enhancement and Article Contribution: Identified and resolved tool bugs, leading to multiple
  • enhancements, and contributed solutions to Cadence Support Portal to reduce customer dependency on AEs which enhance organization’s productivity.
  • Expanding Adjacency: Also supported the signoff STA requirements and addressed multiple issues, and
  • received special recognition and appreciation from management.
  • Effective Collaboration: Through effective collaboration with product engineering teams, TI SOCV libraries
  • were successfully validated which facilitated the smooth migration of designs, contributing to multiple tapeouts.
Artificial Intelligence (AI)Optimization TechniquesCustomer SupportTool Enhancement

Aricent

Physical Design Engineer

Sep 2018Jan 2019 · 4 mos · Bangalore Urban, Karnataka, India · On-site

  • Worked on 14nm Kuiper Project, owning multiple blocks with responsibilities including the complete PNR
  • implementation.
  • Gained experience on resolving DRCs with Caliber tool and managing Timing and Functional ECOs to address timing violations and quality issues.
Artificial Intelligence (AI)DebuggingPhysical Design

Intel corporation

Digital Design Engineer

Jul 2015Jun 2018 · 2 yrs 11 mos · Bengaluru, Karnataka, India

  • Good exposure in backend ASIC design activities.
  • Worked on Ultra High Speed IA Core IP with industry leading process technology.
  • RTL-to-GDS implementation using Synopsys DC and ICC tools.
  • Implemented ECOs to address functional bugs, timing and physical verification violations.
  • Solid Understanding of Static Timing Analysis and timing constraints.
  • Low Power implementation and Functional Verification.
  • Reliability verification.
  • Project# 3 Jan ‘17 – June ‘18
  • Tools Used: Synopsys DCT and ICC, FEV
  • Owned multiple complex Functional Unit Blocks.
  • Responsible to meet the timing targets, power targets, reliability verification and functional equivalence.
  • Started from synthesis of these blocks till the GDS implementation.
  • Contributed in the floorplanning of the design exchange format (def) file for optimum location of ports.
  • Also contributed in the optimization team to enhance the recipe of min delay fixer.
  • Recognized for my contribution in timing fixes which helped other blocks in meeting the timing targets.
  • Project# 2 Apr ‘16 – Dec ‘16
  • Tools Used: Synopsys ICC, FEV
  • Owned multiple complex Functional Unit Blocks.
  • Responsible to meet the timing targets with the manual fixes in ICC.
  • Last mile fixes done to gain in the frequency of the design after taking the silicon feedback.
  • Project# 1 July ’15 – Mar ’16
  • Tools Used: Synopsys ICC, FEV
  • Owned multiple Functional Unit Blocks.
  • Responsible to close the timing targets, power targets, reliability verification and functional equivalence.
  • Manual ECO fixes done using the ICC tool to meet the required targets.
Artificial Intelligence (AI)Optimization TechniquesDigital DesignBackend ASIC Design

Idea cellular ltd

Graduate Engineer Trainee

Jul 2011Apr 2012 · 9 mos

Education

Indian Institute of Technology, Kanpur

Master of Technology (MTech)

Jan 2013Jan 2015

Malaviya National Institute of Technology Jaipur

Bachelor of Technology (BTech)

Jan 2007Jan 2011

DAV Public School

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