A

Aditya S Jagtap

Software Engineer

India8 yrs 7 mos experience

Highly Stable

Key Highlights

Expert in System-on-Chip design and VLSI.
Proven leadership in semiconductor project management.
Fluent in multiple languages enhancing team collaboration.

Stackforce AI infers this person is a semiconductor design expert with strong leadership capabilities.

Contact

Skills

Core Skills

SocVlsi

Other Skills

VerilogLow-power DesignDigital IC DesignFPGAASICVLSI CADMixed-Signal IC DesignSemiconductor DeviceCadence VirtuosoAltera QuartusICEmbedded SystemsApplication-Specific Integrated Circuits (ASIC)Field-Programmable Gate Arrays (FPGA)Integrated Circuits (IC)

About

Senior Physical Design Engineer at NVIDIA with a Master of Technology in VLSI Design from Vellore Institute of Technology. Contributing to advanced semiconductor solutions by leveraging expertise in System-on-Chip (SoC) design, Verilog, and team leadership. Previous experience includes roles at Intel Corporation as a System-on-Chip Design Engineer and Synopsys Inc as a Senior Application Engineer. Academic foundation in Electronics and Telecommunications, combined with proven management acumen, supports a strong record of collaboration and technical problem-solving in the semiconductor domain. Fluent in English, Hindi, and Marathi.

Experience

8 yrs 7 mos

Total Experience

2 yrs 9 mos

Average Tenure

2 mos

Current Experience

Amd

Member of Technical Staff

Mar 2026 – Present · 2 mos · Bengaluru, Karnataka, India · On-site

Nvidia

Senior Physical Design Engineer

Nov 2022 – Mar 2026 · 3 yrs 4 mos · Hyderabad, Telangana, India

VerilogSoCLow-power DesignDigital IC DesignFPGAASIC+13

Intel corporation

System-on-Chip Design Engineer

May 2021 – Nov 2022 · 1 yr 6 mos

Synopsys inc

3 roles

Senior Application Engineer

Promoted

Nov 2020 – May 2021 · 6 mos

Application Engineer II

May 2018 – Nov 2020 · 2 yrs 6 mos

Graduate Engineering Trainee

Oct 2017 – May 2018 · 7 mos

Education

Vellore Institute of Technology

Master of Technology (M.Tech.) — VLSI Design

Jan 2015 – Jan 2017

Prof. Ram Meghe Inst. of Tech and Research , Amravati

Bachelor of Engineering (B.E.) — Electronics and Telecommunications

Jan 2011 – Jan 2014

Acharya Shrimannarayan Polytechnic, Wardha

Deploma — Electronics and Telecommunications

Jan 2008 – Jan 2011

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