May 2019 – Jul 2019 · 2 mos · Redmond, WA

May 2017 – Nov 2017 · 6 mos · Greater Boston Area

Jan 2017 – Jan 2022 · 5 yrs · Greater Atlanta Area

• Graduate research assistant, working with Prof. Tushar Krishna. I am currently working on design and investigation of neuromorphic accelerators. Last semester we designed and developed a microswitch based lightweight interconnection network for deep learning accelerators.

Dec 2015 – Jul 2016 · 7 mos · Bangalore, India

• I was part of the SoC power team.
• My responsibilities included the following:
• 1) Owning the RTL of the power management subsystem of the SoC
• 2) Writing UPF and CPF based power intent spec for the SoC top and immediate partitions.
• 3) Power integrity checks on the SoC across the possible use case corners using the Conformal low power tool (CLP).

Aug 2013 – Nov 2015 · 2 yrs 3 mos · Bangalore, India

• I worked with the SoC integration team. Here's what I did during this period.
• 1) Maintained and delivered the top level Verilog code for 5 Snapdragon SoCs (3 MSMs and 2 MDMs)
• 2) Wrote Verilog code for incremental changes for top level subsystems
• 3) Performed subsystem integration on the chip top level for interrupts, JDR and other control signals
• 4) Developed several in house scripts for design automation.

Feb 2013 – Jun 2013 · 4 mos · Singapore

• I worked with Prof. Thambipillai Srikanthan and Dr. Siew Kei Lim during my internship.
• My contributions to the project were the following.
• 1) Developed drivers, libraries and applications for TI Evalbot
• 2) Ported bare metal libraries to uCOS-III on TI Evalbot
• 3) Ported libraries for uCOS-III to run on Xilinx Zedboard

May 2012 – Jul 2012 · 2 mos · Bangalore, India

• During this time, I had the opportunity to work with the Hardware Apps team.
• My contributions were the following.
• 1) Investigated possible communication protocols for system level use-cases in master-slave DSDA systems
• 2) Designed prototype for a DSDA system by interfacing separate Qualcomm chipsets