Ujjwal Kant — Product Manager
Programming Languages: Perl, Verilog, System-Verilog, C++. ASIC Flow: RTL Design, SoC, Static Timing Analysis, Functional verification, Synthesis, Place and route, Floor-planning, DFT, BIST. EDA Tools: VCS, Design Compiler, Xilinx ISE, ModelSim, NC-Verilog, Cadence Virtuoso. Operating systems: Windows, Linux, Unix.
Stackforce AI infers this person is a VLSI design and verification engineer with a strong focus on ASIC development.
Location: Austin, Texas, United States
Experience: 11 yrs 9 mos
Career Highlights
- Expertise in ASIC design and verification.
- Proficient in multiple programming languages including C++ and Verilog.
- Strong background in EDA tools and methodologies.
Work Experience
Intel Corporation
ASIC Emulation Engineer (3 yrs 4 mos)
Senior GPU System Validation Engineer (1 yr 3 mos)
Senior Design Verification Engineer (1 yr 5 mos)
Design Verification Engineer (3 yrs)
Apple
System Validation Engineer (1 yr 4 mos)
San Jose State University
Graduate Teaching Assistant (Advanced Computer Architecture) (4 mos)
Sandeepani School of VLSI Design
Trainee (5 mos)
ANG Industries Ltd
Graduate Engineering Trainee (7 mos)
NTPC
Summer Intern (1 mo)
Education
Master of Science (MS) at San Jose State University
Bachelor of Technology (BTech) at Rajasthan Technical University