INDRAKUMAR POLISETTY

Software Engineer

Hyderabad, Telangana, India19 yrs 8 mos experience

Highly Stable

Key Highlights

Over 15 years of experience in VLSI industry.
Expert in PDK development and automation.
Proven track record in analog and digital layout design.

Stackforce AI infers this person is a VLSI expert with strong capabilities in PDK development and automation.

Contact

Skills

Core Skills

Pdk DevelopmentAnalogPhysical Design

Other Skills

PDKiPDKCustom PDK DevelopmentAnalog Layout DesignAutomationTest Chip Layout32nm22nmVLSICadenceTCLLayoutpythonPerlCustom Compiler

About

Overall 15+ years of Experience in VLSI industry. ------------------------------------------------------------------------- * 8+ years experience in PDK development and Automation * 1+ years experience in Analog Layout Design and Automation * 3 years experience in Custom Digital Layout Design and Automation ------------------------------------------------------------------------- - Customized tool development for Cadence and Custom Designer - P-cell development in Ciranova, Cadence and Laker - Enhancement scripts for CSR and VSR Auto routers - Rule deck development in Calibre and Assura - Python, SKILL and TCL programming ------------------------------------------------------------------------- - iPDK and Custom PDK development - Analog blocks like bandgap, Rx and Tx - 32nm and 22nm test chip layout - Memory layouts ------------------------------------------------------------------------- Specialties: I always try to automate things to reduce the TAT and QA.

Experience

19 yrs 8 mos

Total Experience

4 yrs 8 mos

Average Tenure

4 yrs 6 mos

Current Experience

Micron technology

2 roles

Principal Engineer

Promoted

Jun 2023 – Present · 2 yrs 11 mos · Hyderabad, Telangana, India

Staff Engineer

Nov 2021 – Jun 2023 · 1 yr 7 mos · Hyderabad, Telangana, India

Synopsys inc

2 roles

Staff Application Engineer

Dec 2020 – Oct 2021 · 10 mos

Senior Application Engineer

Feb 2011 – Dec 2020 · 9 yrs 10 mos

Working on iPDK and custom PDK development.

Pmc-sierra

Layout Design Engg as a contractor

May 2010 – Feb 2011 · 9 mos

Working on Analog blocks like Transmitters and Receivers.

Amd

Layout design engg

Jul 2007 – Jun 2010 · 2 yrs 11 mos

32nm and 22nm test chips.
Done so many skill scripts and pcells in automating the things.

Sankalp semiconductor

Layout Design Engg

Aug 2006 – Feb 2011 · 4 yrs 6 mos

Working as a Analog Layout Design engg and Automation expert.
Played key role in increasing the productivity and efficiency of layout work by automating it.