Indushekhar Benjwal

Director of Engineering

Bengaluru, Karnataka, India27 yrs 1 mo experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Over 25 years of leadership experience in engineering.
  • Expertise in PDK development and ASIC methodologies.
  • Proven track record in managing cross-country teams.
Stackforce AI infers this person is a Semiconductor Engineering Leader with extensive experience in design methodologies and team management.

Contact

LinkedIn

Skills

Core Skills

ManagementPdk DevelopmentPhysical ImplementationDesign PortingBackend Design Methodologies

Other Skills

ASICCustomReliability ValidationPhysical Design SupportProjectsEDAPhysical DesignAnalogCadenceIntegrated Circuit DesignPlace & RouteMixed SignalPhysical VerificationSoCVLSI

About

A motivated and Visionary Leader with over 25 years of commercial experience. Strong leadership skills with understanding of design methodologies; Process Technologies and design issues. Worked in UK, USA, Europe and India for many years and managed the cross-country organizations in UK and APAC. Got expertise in: -Management (Technical, Project, People, Stakeholder) -Building Teams from Scratch -PDK(Process Design Kit) Development and QA -EDA Flow methodologies in ASIC/Custom/RV -Physical implementation of analog/digital/mixed signal design -Porting of analog/mixed signal blocks from one process to another.

Experience

27 yrs 1 mo
Total Experience
13 yrs 6 mos
Average Tenure
15 yrs 8 mos
Current Experience

Intel corporation

3 roles

Director of Engineering

Promoted

Oct 2022 – Present · 3 yrs 6 mos

  • Leading and Managing Design Enablement/PDK (Process Design Kit) Development in Area of ASIC, Custom, RV(Reliability Validation), Runset and Extraction at leading edge technology.
ManagementPDK DevelopmentASICCustomReliability Validation

Sr. Engineering Manager

Promoted

Aug 2012 – Oct 2022 · 10 yrs 2 mos

Tech Lead Design Automation

Aug 2010 – Aug 2012 · 2 yrs

Nxp

2 roles

Backend Architect (Principal Design Methodology Engineer)

Promoted

Apr 2005 – Jul 2010 · 5 yrs 3 mos

  • Lead the team on physical implementation and IP view creation activities.
  • Responsible for design porting from one process to another. eg 180nm to 90nm, 90nm to 65nm, 65nm to 45nm and 65nm to 90nm.
Physical ImplementationDesign Porting

Senior Design Methodology Engineer

Jan 1999 – Mar 2005 · 6 yrs 2 mos

  • Responsible for Backend design methodologies and Physical design support, including developing complex design methodologies.
Backend Design MethodologiesPhysical Design Support

Education

Indian Institute of Technology, Bombay

M.Tech. (Master of Technology) — Microelectronics

Jan 1996 – Jan 1998

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