Jun 2022 – Jan 2025 · 2 yrs 7 mos

Jan 2021 – Jun 2022 · 1 yr 5 mos

May 2018 – Jan 2021 · 2 yrs 8 mos · Bangalore

• Manage Serdes Phy development at Rambus IDC

Apr 2017 – Apr 2018 · 1 yr

• Managed the TCON development at Megachips India design center (Spec to Silicon char). Key macros developed were eDP Phy / High performance PLLs and Oscillators. The team excelled on innovation front and filed multiple patents while driving the architecture for next generation PHY development. Managed the test lab which owned the eDP Phy characterization in multiple products of key customers.

Jan 2015 – Mar 2017 · 2 yrs 2 mos

Feb 2013 – Dec 2014 · 1 yr 10 mos · Bangalore

Apr 2012 – Feb 2013 · 10 mos · Bengaluru Area, India

• Design, debug and silicon characterization of high speed serdes(upto 10Gbps) at the India design center.

Oct 2010 – Mar 2012 · 1 yr 5 mos · Bengaluru Area, India

Oct 2006 – Sep 2010 · 3 yrs 11 mos · Bengaluru Area, India

Oct 2005 – Oct 2006 · 1 yr

• Part of the UWB analog design team. Enaged in design of PLL and high speed current steering DAC.

Jun 2004 – Sep 2005 · 1 yr 3 mos

• Worked on design of PLL based EMI reduction chips, Zero delay Buffers. Involved in silcon characterization and debug of above products.

Jun 2001 – Jun 2003 · 2 yrs

• Worked on PLL based EMI reduction clock chips