Satyam Prasad

Software Engineer

Bengaluru, Karnataka, India5 yrs 7 mos experience

Key Highlights

  • 3+ years of experience in FPGA design.
  • Expert in RTL design for DDR/LPDDR interfaces.
  • Strong background in DFT and integration of digital/analog IPs.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in FPGA and RTL design.

Contact

Skills

Core Skills

Rtl DesignDft

Other Skills

System VerilogVerilogLintRTLAVCLPCDCVerdiPerlUnixC (Programming Language)MATLABVery-Large-Scale Integration (VLSI)Microsoft ExcelIntel Quartus PrimeVHDL

About

Working as a FPGA Silicon Design Engineer at Altera. I have 3+ years of experience in designing and testing complex RTL modules for DDR/LPDDR interfaces. I worked on integrating digital/analog IPs and UPF definition, ensuring high quality design delivery with front-end tools like Lint, CDC, VCLP. Worked on DFT insertion of IO subsystem. I hold a Master of Technology in Electrical Engineering from IIT Bombay and a Bachelor of Technology in Electronics and Communications Engineering from BIT Sindri. I am passionate about learning new technologies and enhancing my skills. My goal is to continue contributing to the advancement of semiconductor technology and innovation.

Experience

5 yrs 7 mos
Total Experience
2 yrs 3 mos
Average Tenure
1 yr 1 mo
Current Experience

Altera

FPGA Silicon Design Engineer

Apr 2025Present · 1 yr 1 mo · Bengaluru, Karnataka, India · Hybrid

  • Design of Chainstop block, handling register configuration in the IO chain using AXI4-Lite interface
  • UPF Definition, Synthesis and Timing Closure
  • Integrating DFT Techniques
  • Working on design flows Lint, CDC, RTLA, VCLP etc.
System VerilogVerilogRTL DesignDFT

Intel corporation

FPGA Silicon Design Engineer

Jul 2022Mar 2025 · 2 yrs 8 mos · Bengaluru, Karnataka, India · Hybrid

  • Designing complex RTL modules like Duty Cycle Correction, LDOs and testing them
  • Working on APB, DDR protocols
  • Designing and testing complex RTL modules for DDR/LPDDR interfaces
  • Integrating Digital/Analog IPs
  • Ensuring high quality design delivery with error free IP releases via front end tools like Lint, CDC, VCLP
SystemVerilogLintRTL DesignDFT

Indian institute of technology, bombay

3 roles

Teaching Assistant

Dec 2021Jun 2022 · 6 mos

  • Introduction to Electrical Engineering: EE113

Teaching Assistant

Jul 2021Dec 2021 · 5 mos

  • Microelectronics Simulation Lab: EE735

Teaching Assistant

Aug 2020Jul 2021 · 11 mos

Education

Indian Institute of Technology, Bombay

Master of Technology - MTech — Solid State Devices

Aug 2020Jun 2022

BIT Sindri

Bachelor of Technology — Electronics and Communications Engineering

Aug 2016Jul 2020

Delhi Public School, Ranchi

AISSCE

May 2014May 2016

Vivekananda Vidya Mandir, Ranchi

AISSE

May 2009Mar 2014

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