Abhishek Gupta

Software Engineer

Bengaluru, Karnataka, India12 yrs 6 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Over 10 years of experience in VLSI Design.
  • Expertise in GPU RTL design and microarchitecture.
  • Proven track record in power firmware development.
Stackforce AI infers this person is a Semiconductor expert with extensive experience in RTL design and verification.

Contact

LinkedIn

Skills

Core Skills

Rtl DesignMicroarchitecturePower Firmware DevelopmentIp VerificationRtl Development

Other Skills

Performance analysisClock ManagementPower ManagementPost-Si BringupDDR-PHY RTL designUVMFunctional CoverageVerification IP designVerilogEmbedded SystemsOOPDigital Image ProcessingMicroprocessorsTurbo CRTL verification

About

Working in Qualcomm, as a GPU RTL Designer. 10+ years of experience in VLSI Design, RTL design and micro-architecture, Debugging, Firmware development, Post Silicon debug.

Experience

12 yrs 6 mos
Total Experience
4 yrs 2 mos
Average Tenure
9 yrs 7 mos
Current Experience

Qualcomm

5 roles

Sr. Staff Engineer

Promoted

Dec 2025 – Present · 5 mos

Staff Engineer

Dec 2021 – Dec 2025 · 4 yrs

  • RTL design and Performance analysis of GPU last level Cache
  • Microarchitecture and RTL Development for GPU Clock Controller
RTL designPerformance analysisMicroarchitecture

Sr. Lead Engineer

Dec 2019 – Dec 2021 · 2 yrs

  • Power Firmware development for GPU
  • Mainly includes :
  • 1. Clock Management
  • 2. Active and Idle Power Management
  • 3. Droop Mitigation
  • 4. Limits Management
Power Firmware developmentClock ManagementPower Management

Senior Engineer

Promoted

Dec 2017 – Nov 2019 · 1 yr 11 mos

  • RTL Design and Post-Si Bringup
  • Responsibe for DDR-PHY RTL design and front-end implementation tasks
  • Continuous debug support to functional verification teams at IP, DDRSS and SoC level
  • DDR Training sequences and Post-Si Bringup
RTL DesignPost-Si BringupDDR-PHY RTL design

Engineer

Aug 2016 – Nov 2017 · 1 yr 3 mos

  • Front End and Post-Si Bringup

Samsung semiconductor india research

Senior Engineer

Apr 2015 – Jul 2016 · 1 yr 3 mos · Bengaluru Area, India

  • IP Verification
  • Responsible for IP Verification of PCIE PHY(PIPE) and sub-controller
  • UVM based verification environment, Constrained Random Test-Cases, SV Assertions and Functional Coverage
IP VerificationUVMFunctional Coverage

Tech vulcan solutions

Associate Engineer

Jul 2013 – Mar 2015 · 1 yr 8 mos · Bengaluru Area, India

  • RTL development of USB 3.0 Device controller
  • Verification IP design for DDR4 interface
RTL developmentVerification IP design

Education

Motilal Nehru National Institute Of Technology

Bachelor of Technology (B.Tech.)

Jan 2009 – Jan 2013

Delhi Public School Aligarh

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