S

Sireesha Vasipalli

Software Engineer

India5 yrs 7 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in design verification methodologies.
  • Proficient in SystemVerilog and UVM.
  • Strong background in silicon design engineering.
Stackforce AI infers this person is a semiconductor design engineer with expertise in verification methodologies.

Contact

LinkedIn

Skills

Other Skills

Universal Verification Methodology (UVM)SystemVerilogVerilogAXIAMBA AHBAPBShell ScriptingFunctional VerificationC (Programming Language)DebuggingRTL CodingPCIePerl Automation

Experience

5 yrs 7 mos
Total Experience
1 yr 10 mos
Average Tenure
3 yrs 9 mos
Current Experience

Amd

2 roles

Sr.Silicon Design Engineer

Promoted

Jul 2024 – Present · 1 yr 10 mos

Silicon design engineer 2

Aug 2022 – Jul 2024 · 1 yr 11 mos

Hcl technologies

Member Of Technical Staff

Jul 2021 – Aug 2022 · 1 yr 1 mo · Bengaluru, Karnataka, India

Amd

Co-op engineer

Oct 2018 – Jul 2019 · 9 mos

Education

Jawaharlal Nehru Technological University, Anantapur

Master of Technology - MTech

Jan 2017 – Jan 2019

Andhra Engineering College

Bachelor's Degree

Jan 2013 – Jan 2017

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