Apr 2025 – Present · 1 yr 1 mo · Bengaluru · On-site

Jul 2021 – Apr 2025 · 3 yrs 9 mos · Bengaluru · On-site

• Worked on Post-Silicon Power ON, Boot/Reset and DFD (Design-for-Debug) for 7nm next-gen multi-die SOC chip.
• Designed and implemented the reset flow FSM for a comprehensive 7nm next-gen multi-die SOC chip, ensuring optimal chip initialization and reliability.
• Collaborated closely with cross-functional teams, including hardware architects, RTL designers, and verification engineers, to define and refine the reset strategy.
• Designed the FSM architecture, specifying state transitions, timing requirements, and reset conditions, while adhering to industry-standard best practices; while optimizing for area, power, and performance.
• Conducted extensive simulations and verification to validate the reset FSM's functionality, identifying and addressing potential issues early in the design process.
• Collaborated with the verification team to develop comprehensive testbenches and test cases, ensuring rigorous testing and verification of the reset logic.
• Maintained clear and well-documented design specifications and organized multiple design reviews, ensuring effective communication with team members and stakeholders.
• Took complete ownership of DFD (Design-for-Debug) architecture and specs.
• Led RTL / collage integration for 7nm next-gen multi-die server SOC; along with generation of post-silicon debug collaterals and assertion-coding.
• Led IP-SOC integration of all debug IPs, implementing trace and trigger fabrics, for two next-gen server SOC chips, along with cleaning up and enabling static checks like spyglass CDC/Lint and caliber/FEV, etc.

Apr 2019 – Jul 2021 · 2 yrs 3 mos · Bengaluru · On-site

• Designed and implemented a brand new IP: DTC (Debug Trace Container), completely from scratch; to be consumed by next-gen 7nm server SOC, working upon all stages of RTL design and static checks like spyglass CDC/Lint, UPF/VCLP, and caliber/FEV, etc.
• Collaborated in RTL delivery of all debug IPs to upcoming 7nm Sierra Forest server SOC, 7nm Granite Rapids server SOC, and Ponte Vecchio GPU.
• Took ownership of entire DFD (Design-for-Debug) IP delivery to SOC: IOSF-SBPA (Intel On-chip Signaling Fabric - SideBand Protocol Aware), DTF (Debug Trace Fabric), DVP (DTF VISA Packetizer), DSO (DTF Source Observer) and ADL (Agent Debug Logic).
• Led conversion of HDK-based methodologies to Cheetah Flow, for synthesis and physical design, for all debug IPs.
• Collaborated in configuration of all 10nm debug IPs to their respective 7nm versions.

Aug 2017 – Apr 2019 · 1 yr 8 mos · Bengaluru · On-site

• Took complete ownership of IOSF-SBPA (Intel On-chip Signaling Fabric - SideBand Protocol Aware) IP; implemented the next-gen version to be consumed by 10 nm server SOC, working upon all stages of RTL design and static checks like spyglass CDC/Lint, UPF/VCLP, and caliber/FEV, etc.
• Conducted extensive simulations and verification to validate the IPs functionality, identifying and addressing potential issues early in the design process.
• Collaborated with the verification team to develop comprehensive testbenches and test cases, ensuring rigorous testing and verification of the logic.
• Maintained clear and well-documented design specifications and organized multiple design reviews, ensuring effective communication with team members and stakeholders.
• Collaborated in RTL delivery of all debug IPs to (already in market) Ice Lake series server SOC chips, Sapphire Rapids server SOC, and Arctic Sound GPU.
• Ramped up and later worked upon entire DFD (Design-for-Debug) architecture: functionality and connectivity of all debug IPs like IOSF-SBPA (Intel On-chip Signaling Fabric - SideBand Protocol Aware), DTF (Debug Trace Fabric), DVP (DTF VISA Packetizer), DSO (DTF Source Observer) and ADL (Agent Debug Logic).
• Collaborated in configuration of all 14nm debug IPs to their respective 10nm versions.