Jul 2020 – Oct 2021 · 1 yr 3 mos

• As a Senior Design Engineer at Xilinx, I specialized in SoC and IP-level verification, driving quality and reliability across complex semiconductor products. My work spanned memory controllers, interconnects, low-power verification, and gate-level simulations, with strong expertise in advanced verification methodologies.
• Key Highlights:
• Verified XRAM memory controllers at both IP and SoC levels, ensuring performance and functional correctness.
• Drove verification of SMMU 3.0 and complex interconnects at the SoC level.
• Led Low Power Verification for entire SoCs, validating boot sequences, power-down modes, and retention features.
• Set up and brought up Gate-Level Simulation (GLS) environments from scratch, with deep expertise in SDF GLS debug.
• Strong exposure to assertions (SVA), functional & code coverage, regression management, and full-chip verification testbenches.
• Worked extensively on system buses (APB, AXI) and contributed to system-level debug.
• Proficient in SystemVerilog with hands-on experience in VMM, OVM, and UVM methodologies.

Dec 2017 – Jul 2020 · 2 yrs 7 mos

• As a Design Engineer II, I contributed to SoC verification and automation, focusing on reset, register access, low-power flows, and memory verification. This role strengthened my foundation in verification methodologies and prepared me for more complex responsibilities in senior roles.
• Key Highlights:
• Developed and automated reset checks and register access tests.
• Contributed to low-power verification and gate-level simulation.
• Performed XRAM verification at the IP level.

Nov 2016 – Dec 2017 · 1 yr 1 mo · Hyderabad, Telangana, India · On-site

• At Microsemi, I worked on IP verification for high-security FPGA/SoC solutions designed for defense, aerospace, communication, and automotive sectors. My focus was on delivering robust and reliable IPs using industry-standard methodologies.
• Key Highlights:
• Verified Smart Bit Error Rate Tester (BERT) and Quad Data Rate (QDR) SRAM memory controller using UVM.
• Performed package testing using Libero toolchains.
• Contributed to building secure, flash-based FPGA/SoC platforms for mission-critical applications.

Jun 2014 – Nov 2016 · 2 yrs 5 mos · Hyderabad, Telangana, India · On-site

• At MosChip, I began my career in ASIC and SoC verification, contributing to defense-grade systems and healthcare innovations. I gained hands-on expertise across low-power flows, GLS, and IP verification, laying a strong technical foundation for my later roles in semiconductor and wearable technologies.
• Key Highlights:
• Verified counters (RTC, DT, WDT), Global Navigation Satellite subsystem, NIC-TZAC, Cortex-A9 processor, and power/clock controllers in a high-end ARM-based SoC for defense applications.
• Performed low-power verification using MVSIM and MVRC tools, along with GLS verification for the full SoC.
• Led IP verification of High-Speed Serial Trace Port supporting multiple data rates.
• Contributed to IP verification of a DNA sequencing platform, supporting next-generation healthcare technology.

May 2014 – Jun 2014 · 1 mo

• PCS layer design and verification

Nov 2013 – Apr 2014 · 5 mos

• Digital, Perl , Verilog , System Verilog , UVM