Mahesh K

Product Engineer

Bengaluru, Karnataka, India12 yrs 11 mos experience

Highly Stable

Key Highlights

Expert in semiconductor verification and validation.
Proven track record in NAND Flash Memory projects.
Strong background in embedded systems and microcontroller programming.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in embedded systems.

Contact

Skills

Core Skills

VerificationSecurity IpNand Flash MemoryChip DesignIp Development

Other Skills

8051 MICROCONTROLLERAXI VIP configurationC AND C++ PROGRAMMINGCoverage closureDebugging assertion failuresEmbedded CEmbedded SystemsFPGAFeature EnhancementsFunctional Coverage ClosureJTAG Verification IP integrationLOGIC DESIGNLatency Module implementationMICROPROCESSOR 8086ModelSim

Experience

Amd

Member of Technical Staff

May 2024 – Present · 1 yr 10 mos

Contributing to Security IP (SECIP) verification at the subsystem level, ensuring secure and robust connectivity across multiple cores and microprocessors.
Verified complex scenarios including memory region access controls, interrupt routing/handling, and secure data transfer flows, significantly improving subsystem reliability and functional robustness

Security IP verificationsubsystem level verificationmemory region access controlsinterrupt routingsecure data transferVerification+1

Samsung electronics

Associate Staff Engineer

Dec 2019 – Apr 2024 · 4 yrs 4 mos · Bangalore

Project: NAND BM Verification
● Led Functional Coverage Closure for NAND Flash Memory verification.
● Developed and enhanced Test Cases for various NAND configurations (SDP, DDP, QDP).
● Performed regression testing and debugging for all test scenarios.
Project: NVMe Controller (Host DMA Verification – Enterprise & Client)
● Implemented Scoreboard Updates & Feature Enhancements, ensuring accurate
verification of NVMe controllers.
● Verified New RTL Releases and ensured comprehensive Functional Coverage Closure.

Functional Coverage ClosureTest Cases developmentregression testingdebuggingScoreboard UpdatesFeature Enhancements+2

Sasken technologies limited

Engineer - Chip Design Advanced

Aug 2018 – Oct 2019 · 1 yr 2 mos · Bangalore

1) Debugging assertion failures and to Configure the AXI VIP in order to create error scenarios that helps to increase overall Functional Coverage
2) Integration of JTAG Verification IP into UVM sub block environment and simulating with C Program tests
3) Implementation of Latency Module to work with AXI interface for measuring performance with Control NOC and Data NOC connectivity

Debugging assertion failuresAXI VIP configurationJTAG Verification IP integrationLatency Module implementationChip DesignVerification

Innovative logic

ASIC IP Verification Engineer

Sep 2015 – Aug 2018 · 2 yrs 11 mos · Bangalore

1) Testbench Development of in-house VIP and 3rd party VIP for USB 2.0 and USB 3.0
2) Worked on Coverage closure and IP Release for customers
3) Involved in doing Regression and Failure Analysis of USB Testcases

Testbench DevelopmentCoverage closureRegression AnalysisVerificationIP Development

Hi power support private limited

Senior Technical Support Engineer

Mar 2015 – Sep 2015 · 6 mos · India

C cubed solutions

Technical Support Representative

May 2014 – Mar 2015 · 10 mos · Bangalore

Tech Support for OS Related Issues.

Rv college of engineering

RESEARCH SCHOLAR

Jan 2013 – Apr 2014 · 1 yr 3 mos · BANGALORE

Worked as Research Scholar in RVCE, Bangalore.
To Develop Solar Cell of layers, P,i, and N of 10 Cm Dia and to do research to find the methods to increase the efficiency of solar cell.