Ankush kumar Dubey

Software Engineer

Bengaluru, Karnataka, India9 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Analog Circuit Design and Quality Assurance.
Proven track record in successful tape-outs at advanced technology nodes.
Strong leadership in project management and cross-functional collaboration.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Analog and Mixed Signal design.

Contact

Skills

Core Skills

Analog Circuit DesignProject LeadershipQuality Assurance

Other Skills

Bandgap ReferencesCadence VirtuosoVirtuoso ADE AssemblerAnalog-to-Digital Converters (ADC)Electronics & CommunicationsVLSIProject PlanningSilicon ValidationReliabilityPower ManagementVerilogASICPerlTCLLinux

About

To learn more and upgrade myself at every stage of life and to build a strong work base which can lead & help me to march to the top in the long run.

Experience

9 yrs 9 mos

Total Experience

3 yrs 3 mos

Average Tenure

7 yrs 6 mos

Current Experience

Intel corporation

Analog Design Engineer

Nov 2018 – Present · 7 yrs 6 mos · India · Hybrid

Working as Senior Analog Design Engineer in Analog and Mixed Signal.

Bandgap ReferencesProject LeadershipAnalog Circuit Design

Altran india pvt. ltd.

Analog Design Engineer - II

Jan 2018 – Nov 2018 · 10 mos · Bangalore

Working as an Analog Design Engineer - II in Analog and Mixed Signal.
Responsible for the tape-out of testchips at TSMC- 16nm technology node.
Designed AC JTAG for SERDES which support IEEE standard - 1149.1 & 1149.6.
Coordinated with Layout Engineers for the Post Layout Simulations.
Responsible for Quality Assurance Check of IPs.
Coordinated with Layout Engineers for the EMIR and Reliability checks for IPs

Cadence VirtuosoVirtuoso ADE AssemblerAnalog Circuit DesignQuality Assurance

Soctronics technologies pvt ltd

Analog Design Engineer

Jul 2016 – Dec 2017 · 1 yr 5 mos · Hyderabad Area, India

Working as an Analog Design Engineer - I in Analog and Mixed Signal.
Responsible for the tape-out of testchips at 22FDSOI, 14LPP & 7LP technology node.
Successfully done the tape-out of Voltage Sensor IP for the testchip at 22FDSOI & 7LP techology node.
Successfully done the tape-out of Thermal Sensor IP for the testchip at 22FDSOI & 14LPP techology
node.
Responsible for Architecture selection for Voltage Sensor, Thermal Sensor IP.
Responsible for block level Designing to Integration of IP.
Responsible for Power, Performance and Area for Voltage & Thermal Sensor IP.
Designed standard cells for AMS blocks.
Coordinated with Layout Engineers for the Post Layout Simulations.
Coordinated with Custom Layout Engineers, Physical Design Engineer for floorplan to chip level Integration.
Responsible for Quality Assurance Check of IPs.
Coordinated with Layout Engineers for the EMIR and Reliability checks for IPs.

Bandgap ReferencesCadence VirtuosoAnalog Circuit DesignQuality Assurance

Soctronics

Intern

Jul 2015 – Jul 2016 · 1 yr · Hyderabad Area, India

Worked as an intern in Analog Design on 22FDSOI, 65nm, 55nm & 90nm technology node.
Involved in Design & Tape-out AADC IP for the testchip at 22FDSOI techology node
Done designing and layout of project entitled as “Low power Low Voltage SAR ADC for Industrial Application” as a part of internship for M.Tech project
Undergone 6 months extensive professional training at VEDAIIT, Hyderabad as an part of internship.
1. Scripting Languages (Perl, TCL, C-shell)
2. Fundamentals of Analog & Mixed Signal Design.
3. Basics of Layout.

Cadence VirtuosoAnalog-to-Digital Converters (ADC)Analog Circuit Design