Mayank Kapadiya — Product Engineer

Experienced DFT Engineer with a demonstrated history of working in services industry. Skilled in shell scripting, SPICE, CMOS, EDA, and RTL Coding. Strong engineering professional with a M.Tech. focused in VLSI Design from NIRMA University. DFT activities: DRC check for RTL using Spyglass MBIST Insertion using LV flow/Tessent shell Scan Insertion using DFT compiler/Tessent shell DFT Verification(With/without Timing) using VCS/NCSIM Pattern Generation using TetraMAX/Testkompress/Modus ATPG Coverage improvement Expertise in IEEE 1687, 1500 and 1149.1 Publications: M. Kapadiya, N. Devashrayee "An analysis to determine best adder circuit for high-speed memory BIST" Journal of Engineering & Technology, GIT, 2012. Published Article in Snug-2019 on “Effective implementation of Shared CODEC to reduce overall DFT pin requirement” Published blog in Desing & Reuse: https://www.design-reuse.com/articles/45753/reducing-dft-footprints-a-case-in-consumer-soc.html

Stackforce AI infers this person is a DFT Engineer with expertise in VLSI and semiconductor testing.

Location: Bengaluru, Karnataka, India

Experience: 14 yrs 8 mos