Viren Bansal — Engineering Manager

• 20 years experience in ASIC Design and Verification. Expertise in all frontned activities including RTL development and integration, design verification, Power and debug architecture, Synthesis, LEC, CDC/Lint checks, IO interface timing Closure • Extensive experience in Multi-Million Gate Chip Execution from Specification, Architecture, RTL Design, design verification and Post Silicon Bring-Up • Experience in working with multi-functional teams in technical leadership roles, coordinating design activities, resolving technical issues, brainstorming solutions and creating/tracking development schedules • Recognize strength in team building and managing team members Specialties: SoC/IP RTL Design and integration (including quality checks like CDC,Lint etc) Synthesis,LEC and ECO implementation Design Verification (simulation, Formal, CLP, Post silicon bringup) Timing Closure (IO interfaces) Architecture (Power, Debug, bus interfaces)

Stackforce AI infers this person is a seasoned ASIC Design and Verification expert with extensive experience in semiconductor industry.

Location: Bengaluru, Karnataka, India

Experience: 25 yrs 3 mos