Teja Reddy Sadana — Software Engineer

I bring 7 years of experience enabling complex digital designs across advanced process nodes, with hands-on ownership from RTL to GDSII. My expertise spans block-level and full-chip implementation, having worked on a wide variety of high-performance designs including CPUs, GPUs, and SoCs. Proficient in deploying and supporting advanced EDA tools such as Fusion Compiler, PrimeTime, Innovus, DSO.ai, and Phoenix, I focus on: RTL synthesis and timing constraint development Static Timing Analysis (STA) and ECO closure Floorplanning, place & route, and physical verification Power-performance-area (PPA) optimization and convergence Flow bring-up, automation, and tool benchmarking I’ve collaborated closely with design and CAD teams to resolve tool issues, customize flows, and improve implementation quality and turnaround time. My work ensures predictable design closure with first-pass success across multiple IPs and subsystems. I’m passionate about scalable implementation strategies, design enablement, and pushing the limits of digital design at advanced nodes.

Stackforce AI infers this person is a Digital Design Engineer specializing in EDA tools and SoC implementations.

Location: Bengaluru, Karnataka, India

Experience: 7 yrs 9 mos