indranil basu

Director of Engineering

Bengaluru, Karnataka, India22 yrs experience

Most Likely To SwitchHighly Stable

Key Highlights

Stackforce AI infers this person is a Semiconductor Design Expert with extensive experience in VLSI and SoC development.

VlsiSocMemory Compilers

EDACMOSStatic Timing AnalysisICSRAMROMPower AnalysisVery-Large-Scale Integration (VLSI)System on a Chip (SoC)

15+ years of experience in custom circuit design (SRAM's/ROM/Custom hard IP's)

22 yrs

Total Experience

7 yrs 4 mos

Average Tenure

7 yrs 9 mos

Current Experience

2 roles

Promoted

Apr 2022 – Present · 4 yrs 1 mo · Hybrid

Leading a 15 member team of circuit and physical design engineers to deliver High speed Cache memories and Hard IP's for GPU die for different Integrated & Discrete graphics program
Responsibilities include people management of Bangalore Team, Mentoring the TFM development for IP design and tracking of IP delivery schedule for different programs, technical guidance and review of the IP's under development and interactions with the structural design team to resolve issues related to IP integration as well as Post silicon team to debug IP related post silicon issues

VLSISoCEDACMOSStatic Timing AnalysisIC+1

Aug 2018 – Apr 2022 · 3 yrs 8 mos · Hybrid

Special circuit development for graphics applications - small signal arrays, large signal arrays L1 & L2 cache memories, ring oscillators, glitch free muxes, voltage droop monitors etc.

VLSISoCEDACMOS

3 roles

Promoted

Jul 2013 – Aug 2018 · 5 yrs 1 mo

My professional expertise is in the area of memory compilers (Single & dual port RAM's & ROM) involving architecture definition and timing and power analysis. Apart from this, I also work on statistical optimisations for SRAM/ROM reliability analysis, and silicon debug of SRAM/ROM failures. My current interests are in low power SRAM/ROM for IOT applications and methodology to estimate SRAM aging for automotive applications

Memory CompilersSRAMROMPower Analysis