Sep 2020 – Sep 2024 · 4 yrs · Bengaluru, Karnataka, India

• Responsible for CPU validation of next generation Intel CPU features.
• Role includes working with global stakeholders to understand Architecture and Microarchitecture design specifications, defining validation strategy, validation plan, test content & coverage plans.
• Validation responsible for new advance ISA features of Intel x86 like FRED (Flexible Return and Event delivery), APX (Advance Performance extension), Patching mechanisms, Microcode features and SEAM (Secure enable mode).
• Global lead for x86 architectural coverage for new and legacy CPU ISA features
• Working RIT tool teams for content requirements for CPU features
• Mentoring team with understanding on CPU features, microarchitecture, and failure debugging of X86 Core

Feb 2019 – Sep 2020 · 1 yr 7 mos · Bengaluru, Karnataka, India

• Architecture verification for ARM V8a CPU architecture

Apr 2016 – Jan 2019 · 2 yrs 9 mos · Bengaluru, Karnataka, India

• AMD64 x86 Zen/Valhalla Core verification
• Test plan owner for AMD64 x86 core’s Streaming Performance Monitor Counter feature.
• Development of UVM components for feature verification.
• Responsible defining functional coverage plan and writing functional coverage for feature.
• Responsible for stimulus creation using x86 assembly and AMD internal random exercisers.
• Cross functional role for interacting with different Unit level owners and SOC team for feature verification.
• Responsible for enhancement and maintenance of System Model verification component

Jul 2015 – Mar 2016 · 8 mos · Greater Noida

• Development of modular UVM SV based platform for ARM A53 based CPU subsystem
• 1) Responsible for development of a generic UVM based generic environment.
• 2) Development of UVM custom agents to interact with subsystem.
• 3) Deployment of standard AMBA VIP agents provided by EDA vendors.
• 4) Creating virtual sequences to correlate all custom and AMBA UVM agents.
• 5) Parameterized environment of handle different ARM CPU subsystems like single cluster or dual cluster systems, single core or multi core systems, with or without GIC systems.
• 6) Capable of running software centric (C/ASM) tests
• 7) Includes coresight debug trace verification support.
• 8) Development of System level scenario verification.
• 9) Low power and netlist (Zero-delay and SDF annotated) simulation support.

Feb 2012 – Jun 2015 · 3 yrs 4 mos · Greater Noida

• Automated Formal verification methodology deployment on ARM A7/A53 based CPU subsystem
• 1) Developed fully automated flow for Formal verification, which capture design information from specification
• 2) Generates setup for Jasper based Formal verification flow which includes run scripts, design assumptions and reports generation.
• 3) Methodology is capable of performing following tasks,
• ==> Interface verification - All AMBA interface bridges ACE, AXI4, AXI3, APB and ATB are verified using IPK or ABVIP JasperGold flow. Supports both protocol verification and scoreboarding.
• ==> Register Verification - Jasper CSR (control and Status register) based register verification. Captures register information from IPXACT based XML and uses IPK or ABVIP AMBA driver to verify the registers.
• ==> UPF clamp value check - Compare and reports design Reset value vs UPF Clamp values.
• ==> Embedded Assertion Support - Verifies user defined custom System Verilog assertion based VIP.
• Low power verification of A7 based CPU Subsystem
• a) Responsible for Low Power Verification of multi core ARM based CPU Subsystems.
• b) Development of simulation based environment for Power Aware verification of RTL and NETLIST Level.
• c) Development of tests to cover all possible low power scenarios ARM CPU subsystem
• ST MBIST test and repair IP Verification
• 1) Responsible for IP Level functional verification of ST MBIST Test and Repair Solutions across different technologies C45,C28, M55 etc.
• 2) Responsible for developing constraint random verification environment fort RTL and back annotated simulations.
• 3) Responsible for developing SV Assertions for protocol verification and functional coverages.

Oct 2010 – Jan 2012 · 1 yr 3 mos · Greater Noida

May 2007 – Sep 2010 · 3 yrs 4 mos · Noida Area, India