sucharitha pathipati

DevOps Engineer

India12 yrs 10 mos experience

Highly Stable

Key Highlights

12 years of experience in ASIC verification.
Expertise in UVM and SystemVerilog.
Led critical SOC verification projects at AMD.

Stackforce AI infers this person is a highly skilled ASIC Verification Engineer with extensive experience in semiconductor design and verification.

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Skills

Core Skills

Functional VerificationSystemverilogSoc VerificationDebugging

Other Skills

UVMAssemblyVerilogCore microcode instructionsFull chip randomizationSVVHDLJavaCMatlabMicrosoft OfficeEmbedded SystemsModelSimField-Programmable Gate Arrays (FPGA)Very-Large-Scale Integration (VLSI)

About

~12 years of experience as ASIC verification Engineer - Skilled in Assembly, Verilog, Systemverilog, UVM, C++, perl. Strong engineering professional with a Post Graduation focused in Electronics and Instrumentation from NIT Warangal.

Experience

12 yrs 10 mos

Total Experience

9 yrs

Average Tenure

3 yrs 10 mos

Current Experience

Intel corporation

Validation Engineer

Jul 2022 – Present · 3 yrs 10 mos · Hyderabad, Telangana, India · Hybrid

Owning reset functional verification.
Writing testcases/testbench in UVM based environment.
Ensure quality met by meticulous reviews with stakeholders.
Successfully migrated from one flow to another.

Functional VerificationUVMSystemVerilog

Amd

SOC Verification

Jul 2013 – Jul 2022 · 9 yrs · Hyderabad Area, India · On-site

Owned critical test plans like RAS, SKINIT, MSR/CSR, CPUID.
Executed critical bring-ups on/ahead of time (Multi core and Multi thread enablement).
Proficient in assembly coding.
Good at understanding core microcode instructions.
Debugging of critical signatures.
Very good at debugging in Verdi.
Lead regressions in core data path.
Worked on full chip randomization.
Owned Initialization of IO chiplet.