Vivek Prakash Sahu

Software Engineer

Bengaluru, Karnataka, India8 yrs 2 mos experience

Highly Stable

Key Highlights

6+ years as an Analog Design Engineer
Expert in SERDES design across multiple nodes
Leadership experience in academic and professional settings

Stackforce AI infers this person is a highly skilled Analog Design Engineer with expertise in microelectronics and VLSI.

Contact

Skills

Core Skills

SerdesAnalog Integrated Circuit DesignLeadershipAnalog Layout

Other Skills

PCBPhase-Locked Loop (PLL)Digital ElectronicsVerilogCadence VirtuosoMATLAB

About

Full time working professional, with Master’s Degree in Microelectronics and VLSI having 6+ years of experience as an Analog Design Engineer. Proficient in designing SERDES blocks in 3nm, 10nm, 22nm, 40nm, 90nm nodes. Hands on design cycle from TFE stage to sign-oﬀ and Correlation of Post Silicon Data. Major area of work has been : * PLL Design. * High Speed TIA/DRV design for Optical Links(100G/200G). * PMIC Design * Data Converters Circuits Design. ( DACs & SAR-ADC)

Experience

8 yrs 2 mos

Total Experience

3 yrs 7 mos

Average Tenure

1 yr 1 mo

Current Experience

Mediatek

Staff Analog Design Engineer

Apr 2025 – Present · 1 yr 1 mo · Bengaluru, Karnataka, India · On-site

Staff Analog Design Engineer in Analog Circuit Design group :-
AIP lead for TX-MOD.
Multiple Output Driver (VM, 2TAIL, CML ) Design.
Clock Driver Design.
Phase Interpolator calibration circuit Design.
PLL Design (3 stage Ring VCO ) in RX chain.

SERDESPCBAnalog Integrated Circuit Design

Intel corporation

Senior Analog Design Engineer

Jun 2019 – Apr 2025 · 5 yrs 10 mos · Bengaluru, Karnataka, India · Hybrid

Analog Design Engineer in Integrated Silicon Photonics(IPS-DCAI) Group :-
1.6T/200G/8-Channel TIA/DRV design in RF chain.
SAR-ADC design, 12-bit, 10 MSPS.
IDAC-9b, RDAC-8b, CDAC-12b Design.
32G-8x8/2T CWDMA, TIA/DRV/TCU design.
POR,LDO,BGR,OSC,PD-AMP Design.

Analog LayoutAnalog Integrated Circuit Design

Indian institute of technology, kharagpur, mmm hall

2 roles

Second Senate Member ( SSM)

Promoted

Sep 2018 – Sep 2019 · 1 yr

Actively led a hall of 2000+ members.
Organised multiple events and actively worked on improving the hall culture throughout my tenure.

Leadership

Teaching Assistant

Apr 2018 – Apr 2019 · 1 yr

Conducted labs on analog circuits and layouts.
Assisted faculty on planning, preparation and evaluation of exams.

Analog Layout

Airtel

Internship

Dec 2014 – Jan 2015 · 1 mo · Lucknow, Uttar Pradesh, India

*During the Training Period I worked on the project titled "GSM FUNDAMENTALS" under the guidance of Mr. Sanjay Gupta - MW Planning Head , Network Bharti Airtel Ltd.