Raushan Kumar — Software Engineer

• Good understanding of RTL to GDSII flow and specifically hands-on experience in various stages of APR flow. • Knowledge on Logic Design, Static Timing Analysis (STA), Physical Design flow, Linux, Perl, TCL and Python. • Experience in block level implementation of an ASIC in 16nm to 3nm technology. • Interpreting timing reports at each stage of APR flow, identifying the cause for timing violations, and fixing them. • Tools: IC Compiler II and PrimeTime from Synopsys •Experience in owning tape-outs of blocks using PV sign-off tools such as Calibre. • Experience of working in technology nodes ranging from 16nm to 3nm using ICC2 and Innovus tools. • Experience in planning & executing custom routes for noise prone analog nets for better performance of the chip. • Good Knowledge in other Physical Design flow stages like Floor planning, Place and Route, CTS, Timing Analysis, IR Drop Analysis. • First-hand experience in PV fixing, solved issues related to: - LVS, IR, EM, LatchUp, DRC, Antenna (N-well and Gate) & PDN {C2I & Dynamic} issues in both Block level and TOP level. • Experienced in owning tape-outs of Blocks/Chips and integrate implementation environment components utilizing advanced flows and latest P&R tools. • Experienced in rule deck development and customization. • Highly adaptable to all kinds of environment. • Always looking to improve skills and grow with the organization.

Stackforce AI infers this person is a Semiconductor Physical Design Engineer with expertise in automation and verification.

Location: Bengaluru, Karnataka, India

Experience: 8 yrs 9 mos