Tushin Shrotriya — Software Engineer
I am currently working on SoC RTL design and integration. Prior to this, I have 3+ years of experience as a physical design (PD) sign-off engineer for low power VLSI and formal verification. I have worked on Cadence Conformal Low Power tool and Cadence LEC tool.
Stackforce AI infers this person is a VLSI design engineer with expertise in low power design and formal verification.
Location: Bengaluru, Karnataka, India
Experience: 10 yrs 8 mos
Career Highlights
- Expert in SoC RTL design and integration.
- 3+ years in low power VLSI and formal verification.
- Proficient with Cadence Conformal Low Power and LEC tools.
Work Experience
Qualcomm
Staff Engineer (5 mos)
Senior Lead Engineer (3 yrs)
Senior Engineer (2 yrs 11 mos)
Engineer (2 yrs 5 mos)
Dhirubhai Ambani Institute of Information and Communication Technology
Teaching Assistant (1 yr 10 mos)
Sofcon Systems India Private Limited
Trainee (1 mo)
airtel
Intern (1 mo)
Education
Master of Technology (MTech) at Dhirubhai Ambani Institute of Information and Communication Technology
Btech at Sir padampat singhania university
Higher Secondary Education. at St.Thomas convent
Higher Secondary Education at St.Thomas convent