Akash Nagaria

Software Engineer

Bengaluru, Karnataka, India2 yrs 9 mos experience
Highly Stable

Key Highlights

  • Expertise in RTL-to-Gate synthesis for advanced SoC IPs.
  • Hands-on experience with synthesis constraint development and logic optimization.
  • Currently enhancing skills in ASIC Synthesis and STA.
Stackforce AI infers this person is a Semiconductor Design Engineer with a focus on ASIC and SoC development.

Contact

LinkedIn

Skills

Core Skills

Physical Aware SynthesisLogic Synthesis

Other Skills

Conformal LECConformal low powerLow-power DesignObject-Oriented Programming (OOP)Functional CoverageHardware VerificationSystemVerilogAssertion Based VerificationUniversal Verification Methodology (UVM)Functional VerificationCode CoverageCoverage AnalysisSynopsys Design CompilerPython (Programming Language)MATLAB

About

Engineer with hands-on experience in RTL-to-Gate synthesis for advanced SoC IPs (5nm/4nm). Skilled in synthesis constraint development, logic optimization, and quality checks (LEC, CLP, SDC, ERC). Currently strengthening my expertise through advanced courses in ASIC Synthesis, STA, and PD, while actively seeking opportunities as a Synthesis Engineer.

Experience

2 yrs 9 mos
Total Experience
2 yrs 9 mos
Average Tenure
2 yrs 9 mos
Current Experience

Mediatek

2 roles

Senior Engineer

Jul 2023 – Present · 2 yrs 9 mos

Conformal LECConformal low powerPhysical Aware SynthesisLogic Synthesis

Graduate Technical Intern

Jul 2022 – Jul 2023 · 1 yr

Education

National Institute of Technology Rourkela

Master of Technology - MTech — VLSI and Embedded Systems

Jan 2021 – Jan 2023

Bhilai Institute of Technology (BIT), Durg

Bachelor of Engineering - BE — Electrical Engineering

Jan 2015 – Jan 2019

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