Srinu Korada

Software Engineer

Hyderabad, Telangana, India8 yrs experience
Highly Stable

Key Highlights

  • Expert in Silicon Design and Physical Verification.
  • Proficient in RDL implementation and Full Chip PV.
  • Strong scripting skills in Calibredrv and SVRF.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Verification and RDL implementation.

Contact

srinukorada786@gmail.comLinkedIn

Skills

Core Skills

Silicon DesignFull Chip PvRdl ImplementationIo PlanningElectrical Rule CheckingLayout VerificationPhysical Verification

Other Skills

Pegasus Design ReviewPegasusBump planningRDL routingPower RDL generationRDLSVRF scriptingDensityDesign for ManufacturingSoft checkCalibredrv ScriptingAntenna CheckElectrical Rule Check(ERC)TVFCalibredrv

Experience

8 yrs
Total Experience
2 yrs 2 mos
Average Tenure
1 yr 3 mos
Current Experience

Amd

Sr Silicon Design Engineer

Feb 2025 – Present · 1 yr 3 mos · Hyderabad, Telangana, India

Pegasus Design ReviewPegasusBump planningRDL routingPower RDL generationRDL+26

Cadence design systems

Design Engineer 2

Jan 2024 – Feb 2025 · 1 yr 1 mo · Hyderabad, Telangana, India

  • Full Chip PV.
  • RDL implementation, IO Planning and Bump planning.
PegasusIcc2RDL routingInnovusIO planningBump planning+3

Soctronics

4 roles

Engineer 2

Promoted

Mar 2022 – Dec 2023 · 1 yr 9 mos

  • RDL implementation (FCRDL) in AMD flow.
Calibredrv ScriptingRDLSVRF scriptingInnovusIO planningRDL Implementation

Engineer 1

Promoted

Mar 2021 – Mar 2022 · 1 yr

  • Full chip PV issues debugging and fixing.
Design for ManufacturingFull Chip PVAntenna CheckSoft checkDensity

Engineer trainee

Promoted

Mar 2020 – Mar 2021 · 1 yr

  • Worked in fixing Block level PV issues with high congestion.
Electrical Rule Check(ERC)Calibredrv ScriptingIC compiler toolAntenna CheckTVFElectrical Rule Checking

Junior Engineer trainee

Dec 2018 – Mar 2020 · 1 yr 3 mos

  • Debugging PV issues and Fixing in Tile/Block level
calibreLayout Versus Schematic (LVS)CalibredrvIC compiler toolSVRFLayout Verification

Veda iit

Physical Verification Engineer

May 2018 – Dec 2018 · 7 mos · Hyderabad, Telangana, India

  • Trained in Physical Verification
Perl languageCadence Virtuoso Layout EditorTCLDesign Rule Checking (DRC)Shell ScriptingPhysical Verification

Education

MIT School of Distance Education

PGDM in Project Management

Jan 2023 – Oct 2024

Acharya Nagarjuna University

Bachelor of Science - BSC — Electronics

Jun 2019 – Aug 2022

Andhra polytechnic Kakinada

Diploma — Electronics and communication Engineering

Jan 2015 – Jan 2018

ZPHS School Sirlapalem Visakhapatnam

SSC

Jun 2011 – Apr 2015

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