P

PAVITHRA MUTHUKUMAR

Software Engineer

Tamil Nadu, India4 yrs 1 mo experience
Highly Stable

Key Highlights

  • Expert in DFT implementation and verification.
  • Proficient in BIST pattern generation and simulations.
  • Strong background in semiconductor engineering.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in DFT and BIST methodologies.

Contact

Skills

Core Skills

Semiconductor EngineeringDft

Other Skills

BISTScan InsertionAutomatic Test Pattern Generation (ATPG)ATPG synopsis tetramaxCoverge improvementScan pattern validationOCCGLS - Xcelium- Questasim- VerdiIJTAG insertionICL pattern validationTDRMemory TestMBIST insertionMBIST pattern validationSystem on a Chip (SoC)

About

Passionate VLSI Design Engineer with knowledge on Design for Testability (DFT) implementation and verification for IPs and SoCs.

Experience

4 yrs 1 mo
Total Experience
1 yr 8 mos
Average Tenure
--
Current Experience

Amd

Design Engineer II (DFT consultant)

Apr 2024Aug 2024 · 4 mos

  • SMS and LARR BIST tile level patten generation and simulations
DFT

Stmicroelectronics

Design Engineer I (contractor)

May 2023Dec 2023 · 7 mos · Bengaluru, Karnataka, India · Hybrid

BISTSemiconductor Engineering

Tessolve

Design Engineer II

Jul 2021Aug 2025 · 4 yrs 1 mo

BISTSemiconductor Engineering

Education

Government College of Technology, Coimbatore

Master of Engineering - MEng — VLSI Design

Jun 2021Present

Akshaya College of Engineering and Technology

Bachelor of Engineering - BE — Electronics and Communication Engineering

Jun 2019Present

Nirmala Matha Convent Matriculation Higher Secondary School

Bio-Maths

Apr 2015Present

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