Raghavendra M

Product Engineer

Bengaluru, Karnataka, India13 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 10 years of experience in DFT domain.
Expert in scan insertion and ATPG pattern generation.
Proficient in using Tessent for DFT verification.

Stackforce AI infers this person is a DFT Engineer specializing in semiconductor and electronic design verification.

Contact

Skills

Core Skills

DftJtag

Other Skills

ASICATPGATPG ValidationATPG pattern verificationApplication-Specific Integrated Circuits (ASIC)Architecture DevelopmentAutomatic Test Pattern Generation (ATPG)BISTBoundary ScanComputer ArchitectureDFT Activities for 5G chipDFT Activities for Automotive chipDFT Activities for low power coin cell wearable deviceDFT Activities for mobile deviceDFT Activities for wearable Devices

About

10+ years of experience in DFT domain. SoC/IP level Scan implementation, SPYGLASS checks, Scan insertion with Design Compiler, EDT Generation with Tessent, TPI, Scan DFT timing constraint, ATPG pattern generation for stuck-at & SDC based transition and ATPG pattern validation in stuck-at, transition with Tessent-tool in no-timing & SDF timing simulation, Cell-Aware Test static & Cell-Aware Test Delay, Timing Aware ATPG, Power Aware ATPG with Tessent-tool. Diagnosis symptom with Tessent, Silicon bring up, Shmoo analysis. Reliability tests. MBIST Insertion, BIRA insertion, BISR controller implementation with third party fuse-box along with iJTAG, with Tessent shell and verification of the complete suite, Silicon support. JTAG Insertion, Boundary scan insertion, Verification for DC parametric test. Perl and TCL scripting. DFT Flow building.

Experience

Sivaltech

DFT Engineer

Jan 2021 – Present · 5 yrs 2 mos · India · Remote

Intel corporation

senior DFT Engineer

Nov 2018 – Present · 7 yrs 4 mos · Greater Bengaluru Area · Hybrid

Aricent

2 roles

Senior DFT Engineer

Promoted

Jan 2017 – Nov 2018 · 1 yr 10 mos

1. DFT Activities for wearable Devices
JTAG 1149.1 implementation using Tessent Suite, Validation for the same.
2. DFT Activities for 5G chip
MBIST Implementation, Validation of the same in timing and no-timing.
3. DFT Activities for Automotive chip
Scan insertion, ATPG Validation, TPI for the pattern count reduction, Validation of the patterns in timing and no-timing.
4. DFT Activities for the low power coin cell wearable device
MBIST Implementation architecture development and validation for the same.

DFT Activities for wearable DevicesJTAG 1149.1 implementationDFT Activities for 5G chipMBIST ImplementationDFT Activities for Automotive chipScan insertion+5