Siddhant yadav — Software Engineer

With 11+ years of experience in ASIC verification, I specialize in delivering robust, high-quality verification solutions for complex integrated circuit designs. My expertise spans OVM, UVM, SystemVerilog, Verilog, and C programming, combined with a strong focus on formal verification methodologies to ensure design correctness and reliability. I bring a holistic understanding of hardware architecture and firmware interaction, enabling seamless integration during verification. Over the years, I’ve successfully led numerous IP verification projects, driving methodology excellence and mentoring teams to achieve verification goals efficiently. Core Expertise -Verification Leadership: Extensive experience as IP Verification Lead across multiple projects -Formal Verification: Advanced methodologies for design robustness -Protocol & IP Expertise: -USBPD3.0 -DC-DC & AC-DC converters -Multiphase Controller & Gate Drivers -DMA Controller, DDR4 Controller, DPTX Controller, Crypto IPs -Bus Protocols: AXI, AHB, APB -Specialized Domains: -ROM-only chips -Hardware-firmware coordination -Digital Mixed Signal (DMS) -Mixed Signal Design Verification Automation & Scripting: Perl, Python, Bash, Tcl, Make (Makefile scripting) for workflow automation and efficiency

Stackforce AI infers this person is a highly experienced ASIC verification engineer with strong leadership in complex integrated circuit projects.

Location: Bengaluru, Karnataka, India

Experience: 11 yrs 10 mos