RAJESH BARUA

Product Engineer

Bengaluru, Karnataka, India14 yrs 9 mos experience

Highly StableAI Enabled

Key Highlights

Expert in Server and AI SoC Verification.
Specialist in L3 Cache Coherency Validation.
Strong background in robotics and reinforcement learning.

Stackforce AI infers this person is a Semiconductor Verification Expert with a focus on AI and Server technologies.

Contact

Skills

Core Skills

SocVerificationGraphicsValidation

Other Skills

SoC verificationAI productPost-silicon VectorDVServer SoC VerificationMulti-CPU Interconnect MeshValidation codesGraphics Cache validationVerification collateralVLSIASICVerilogSemiconductorsData StructuresLinux

About

Experienced in Server & AI SoC Verification with Multi CPU Mesh Interconnect. Specialist in Validation of L3 Cache Coherency. Validation experience in building Test benches, BFMs, Scoreboards. Skilled in writing & executing test and coverage plans Solid understanding of developing system level test cases and debugging RTL In-depth knowledge of ASIC Design Flow, System Verilog & constrained verification Experienced in robotics development and reinforcement learning Superior written and verbal communications skills

Experience

14 yrs 9 mos

Total Experience

5 yrs 4 mos

Average Tenure

4 yrs 1 mo

Current Experience

Sifive

2 roles

Principal Engineer

Promoted

Apr 2026 – Present · 1 mo

Senior Staff Engineer

Apr 2022 – Apr 2026 · 4 yrs

Qualcomm

2 roles

Staff Engineer

Dec 2018 – Apr 2022 · 3 yrs 4 mos

Working on SoC verification of AI product over multiple generation.
Engaged with Post-silicon Vector & DV for enabling drivers of AI cores

SoC verificationAI productPost-silicon VectorDVSoCVerification

Senior Lead Engineer

Dec 2016 – Dec 2018 · 2 yrs

experience in Server SoC Verification of Multi-CPU Interconnect Mesh
Developed, participated and reviewed validation codes for efficiency/coverage and executed paradigm shifts needed in Validation execution

Server SoC VerificationMulti-CPU Interconnect MeshValidation codesSoCVerification

Intel corporation

Graphics Hardware Engineer

Aug 2011 – Dec 2016 · 5 yrs 4 mos · Greater Bengaluru Area

Experienced in Graphics Cache sub-system validation.
Developed verification collateral (such as behavioral checkers, coverage monitors, test generators or score-boards) to enable test plan execution.

Graphics Cache validationVerification collateralGraphicsValidation