Jul 2018 – Dec 2024 · 6 yrs 5 mos

• Worked in SoC Power Verification team.
• Developed test-cases to verify Inter Processor Communication and Always ON Sub-System at Soc level.
• Worked on various Power Aware, GLS and SDF simulations.
• Worked on emulating various SoC projects on Fpga. Worked on synthesis, place & route and timing closure on Virtex 7, Ultrascale VU440 devices.
• Worked on clock controller and emulating low speed peripherals.
• Worked on Emulation DV and system simulation on Fpga RTL.
• Languages - System Verilog, Verilog, UVM, C
• Tools - Synopsys VCS, Synplify Pro and Xilinx Vivado
• Protocols - APB, AHB, AXI, SPI, I2C and UART
• Courses/Training -
• Coresight SoC - 400
• Vivado Design Suite: Advanced XDC & Static Timing Analysis

Jul 2018 – Dec 2024 · 6 yrs 5 mos

May 2017 – Jul 2017 · 2 mos · Bangalore

• Worked on generalizing performance analysis framework for all the blocks in SoC having AXI and APB interfaces.