Rohit Jindal — CEO

Profile Summary: ------------------- Passionate, Results-driven, and Team-Oriented Professional with extensive experience in Chip Designing, Verification, Validation, Implementation, HW/SW Co-design, and Project Management. Served variety of Individual contributor and leadership roles in my career, currently leading Verification, Performance, Modeling, Tools and Validation team for next generation CPU Core for Laptops, Desktops and Servers. Pioneered many methodologies and flows which significantly improved design cycle time and quality of validation Key Achievements: ----------------------- - Formed high performing multi-site technical teams from scratch in India and US - Many international research papers on verification and HW/SW Co-design - Project Manager of industry first 6GHz Core - Served as Chairman of Accellera IP-XACT Technical Committee - Speaker and Panelist in many International conferences - Successfully led many key front-end initiatives/flows using AI/ML to improve the quality of design and reduce the design time - Trained many engineers on UVM/SV/C/C++/SystemC/SVA Leadership/ Technical Strength: ----------------------- - Successfully completed Verification/validation of many IPs/SoCs, System Level Architecture/Performance analysis, internal EDA tools and CAD flows development - Good knowledge on CPU Core (x86) and neural processors - Expert in setting up a constrained-random reusable verification environment with portable testcases and stimuli across platforms (IP, Sub-system, SoC) using UVM/OVM/eRM/C++ - Expert in HW-SW Co-design, modeling, developing SystemC TLM based virtual platforms for firmware/sw development and performance analysis -Applying Formal Verification for functional sign-off using leading Formal Verification tools -Improving engineering processes using Agile software development, scrum, JIRA dashboards, confluence pages and Splunk Dashboards - Managing projects/flows end-to-end starting from collecting the requirements, developing roadmaps, writing user stories, working hands-on with engineers, integration with other IPs/flows, managing customers bugs/issues using dashboards, data analytics and generating reports/dashboard for management

Stackforce AI infers this person is a Semiconductor Verification Expert with a focus on CPU architecture and AI/ML methodologies.

Location: Bengaluru, Karnataka, India

Experience: 25 yrs

Skills

Cpu Core Verification
Project Management
Ai/ml
Formal Verification
Performance Modeling
Verification
Functional Verification
System Architecture

Career Highlights

Led verification for industry first 6GHz CPU core.
Pioneered methodologies improving design cycle time and validation quality.
Trained engineers on advanced verification methodologies.

Work Experience

Google

Verification Lead (3 yrs 6 mos)

Intel Corporation

CPU core Verification Director (4 yrs 5 mos)

Qualcomm

Principal Engineer/Mgr (5 yrs 11 mos)

Accellera

Chairman of Accellera IP-XACT TC (1 yr 9 mos)

STMicroelectronics

Sr. Technical Manager (4 yrs 8 mos)

Verification Lead/Engineer (6 yrs 5 mos)

Education

BTech at Punjab Technical University

MS at Birla Institute of Technology and Science, Pilani

Rohit Jindal

CEO

Bengaluru, Karnataka, India25 yrs experience

Highly StableAI Enabled

Key Highlights

Led verification for industry first 6GHz CPU core.
Pioneered methodologies improving design cycle time and validation quality.
Trained engineers on advanced verification methodologies.

Stackforce AI infers this person is a Semiconductor Verification Expert with a focus on CPU architecture and AI/ML methodologies.

Contact

Skills

Core Skills

Cpu Core VerificationProject ManagementAi/mlFormal VerificationPerformance ModelingVerificationFunctional VerificationSystem Architecture

Other Skills

ValidationPerformanceModelingToolsRegression AnalysisPre-Silicon Performance ModelingVirtual PlatformVerification MethodologiesSystemCMLPower EstimationIP IntegrationVirtual PlatformsArchitecture AnalysisTLM

About

Experience

25 yrs

Total Experience

5 yrs 9 mos

Average Tenure

3 yrs 6 mos

Current Experience

Google

Verification Lead

Nov 2022 – Present · 3 yrs 6 mos · Bengaluru, Karnataka, India · On-site

Intel corporation

CPU core Verification Director

Jun 2018 – Nov 2022 · 4 yrs 5 mos · Bangalore

CPU Core Validation Director @Intel: Leading Verification, Validation, Performance, Modeling, and Tools team for next generation CPU Core for Laptops, Desktops and Servers. Team consists of 70+ engineers and using best in class simulation, formal, emulation, post-silicon, and performance measurement environments.
Initiatives @Intel: Developed solution for Regression bucketing using AI/ML unsupervised clustering algorithms and AI/ML model for Bug probability based on code changes, coverage, unit complexity and other variables. Improved Verification quality by deploying Formal verification at unit level.

VerificationValidationPerformanceModelingToolsAI/ML+3

Qualcomm

Principal Engineer/Mgr

Jun 2012 – May 2018 · 5 yrs 11 mos · San Francisco Bay Area

Principal Engineer/Mgr @Qualcomm: Led the team responsible for Pre-Silicon performance modeling, Virtual Platform for mobile chipsets and Verification methodologies. Worked on verification and SystemC based virtual platform for Neural Processor Unit (NPU).
Initiatives @Qualcomm: Power estimation using ML multivariate linear regression model on Virtual Platform. Led the initiative to capture/deliver IP as LEGO and make IP integration seamless at SoC level. Developed a tool to capture Portable Stimulus which can be used on IP, SoC verification and Validation.

Pre-Silicon Performance ModelingVirtual PlatformVerification MethodologiesSystemCPerformance ModelingVerification

Accellera

Chairman of Accellera IP-XACT TC

Sep 2010 – Jun 2012 · 1 yr 9 mos

IP-XACT TC chairman @Accellera: Led WG across 20+ companies to enhance the IP-XACT standard, bigger deployment of IP-XACT and make it IEEE standard. Able to achieve 40% growth in the usage as per the Accellera download counts.

Stmicroelectronics

2 roles

Sr. Technical Manager

Promoted

Oct 2007 – Jun 2012 · 4 yrs 8 mos

Sr Technical Manager @ST Microelectronics: Led System Architecture team for setup box and methodologies/tools team for Functional verification, Virtual Platforms, Architecture Analysis and Platform Automation.
System Initiatives @ST Microelectronics: Developed methodology for creating Virtual Platforms for eSW development. This includes model development using TLM2.0 standard, integration, and porting of eSW. Developed In-house tools to measure performance figures like bus utilization, latency, and throughput using simulation database.

Functional VerificationVirtual PlatformsArchitecture AnalysisSystem Architecture

Verification Lead/Engineer

Apr 2001 – Sep 2007 · 6 yrs 5 mos

Verification Lead/Engineer @ST Microelectronics: Worked on Verification of many IPs like R/W Channel, MES, Keyscan, FDMA using OVM, ePlanner, SVA and coverage metrics.
Verification Initiatives @ST Microelectronics: Developed Vertical Verification flow/Methodology for reusing the testcases across all abstraction levels, TLM, RTL IP, SoC and validation. Developed Internal Tool to capture the register information and generate Register testcases. Deployed OVM/UVM/Metric Driven Verification methodologies in ST for Setup Box Group.

VerificationOVMSVACoverage Metrics