Ramesh Madatha — DevOps Engineer

____________________ -- SoC Testbench Architecting & Development -- Leading SoC/Subsystem Verification -- Verification IP Architecture & Development ____________________ -- SSD Controller Flash/Host Verification -- SSD Controller Host CPU VIP Architecture and Development -- SSD Host Controller Verification Testbench Architecture -- Abstract Firmware Testbench Architecture -- Leading NextGen Protocols - PCIe Gen6.0 and CXL2.0 Verification IP Architecture and Development - NVMe Host Controller IP Formal Verification __________________ -- SOC-WLAN Sub-System level Verification, the verification flow uses UVM Methodology. -- SOC functional Verification using Cache-Resident Self-Testing (CReST) feature, for these Blocks -CPU-x86 Cores -Graphics Processing Unit(GFX), Multi Media Blocks(UVD/VCN/DCN/ISP/ACP), NBIO Connected Blocks. Includes the following activities: -Developing TestPlan, -Infra bringup, -Testcase writing, -Bringing up Functional Paths & Features, -Coverage -TestPlan Closer for Tapeout. Exposer to -SOC/SOC15 Computer Architecture -AXI/AMBA Protocol -SDP/SDF -Wi-Fi/Wireless/WLAN, BT -JTAG -Verilog -SystemVerilog -UVM Methodology -Script Writing in PERL, Shell -VCS Tool, Verdi, nWave Debugging -StimGen Tool

Stackforce AI infers this person is a Semiconductor Verification Expert specializing in SoC and SSD technologies.

Location: Bengaluru, Karnataka, India

Experience: 14 yrs 4 mos