Mohammed Zuraiq

AI Researcher

Bengaluru, Karnataka, India0 mo experience

AI EnabledAI ML Practitioner

Key Highlights

Expertise in PCIe and power management validation.
Developed automated validation scripts for Intel processors.
Strong analytical skills with a focus on performance validation.

Stackforce AI infers this person is a Semiconductor Validation Engineer with a focus on performance and power management.

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Skills

Core Skills

Validation EngineeringPower Management

Other Skills

PCIeAutomationSystemVerilogYocto ProjectPerformance EngineeringSystem ArchitectureSystem on a Chip (SoC)Social SciencesAnalog SemiconductorsMixed-Signal IC DesignOS XHP ProductsCisco Systems ProductsDDR SDRAMX86

About

Completed my Master of Technology in Computer Network Engineering at Manipal Institute of Technology, my most recent role as a Graduate Technical Intern at Intel Corporation has honed my expertise in PCIe, power management, and verification and validation (V&V). My tenure at Intel involved developing test cases for hardware accelerator IPs and contributing to an automation framework, strengthening my technical proficiency and problem-solving skills. During my internship, our team enhanced performance validation processes and successfully handled volume validation activities for two server processors set to launch. My analytical acumen and V&V specialization played a pivotal role in these achievements. I am eager to bring this technical knowledge, alongside my passion for innovation and collaborative spirit, to a forward-thinking team where I can contribute to groundbreaking projects and organizational success.

Experience

0 mo

Total Experience

Average Tenure

Current Experience

Intel corporation

Soc power anf performance engineer

Jul 2023 – Aug 2024 · 1 yr 1 mo · Greater Bengaluru Area · Hybrid

Worked in power and performance testing on high-speed PCIE protocol.
Performance validation of high-speed serial I/O interfaces, such as PCIe IP (Gen-4
& Gen-5), for next-generation Intel Xeon processors, with hands-on experience and
expertise in using high-speed equipment for PCIe testing.
Worked closely with Design, Validation, and Architecture teams to integrate Power
Management and PCIe solutions into Xeon processors, ensuring alignment with
performance goals.
Contributed to Power Management IP, focusing on SoC power measurement and
latency calculations.
Supported post-silicon power and performance validation for Intel server products
such as Xeon.
Developed automated validation scripts for specific workloads.
Worked with different integrated silicon boards for different projects.