Abhishek Srivastava โ Software Engineer
I am a Intern at Intel and a Master's student specializing in VLSI Design from NIT Jalandhar. I have Subject knowledge and technical skills in Verilog, System Verilog , System Verilog Assertion, Embedded C ,C, C++ , TCL , GitHub Physical design flow ,Static time analysis, Clock tree synthesis (CTS),PVT, Synthesis hands-on experience with tools like Xilinx VIVADO and Cadence Virtuoso. GATE-qualified During Internship I involves in creating the Unit Test coverage for uncovered and new functions and mocked the code to simulate HW conditions to meet all flows for secure device manager configuration functions. Debugging using Pre-Silicon RTL simulation bit-stream file on silicon to analysis the waveform and Debugging of faulty Firmware I am enthusiastic about contributing to innovative projects in the semiconductor industry. Eager to connect for job opportunities and discussions on advancing VLSI technology. Let's explore possibilities in the world of VLSI together! ๐๐ผ
Stackforce AI infers this person is a VLSI Design intern with a focus on semiconductor technology and validation.
Location: Jalandhar, Punjab, India
Experience: 1 yr 3 mos
Skills
- Static Time Analysis
Career Highlights
- GATE-qualified with strong VLSI Design expertise.
- Hands-on experience with Xilinx Vivado and Cadence Virtuoso.
- Eager to innovate in the semiconductor industry.
Work Experience
Analog Devices
Manufacturing Engineer (1 yr 3 mos)
Intel Corporation
Post silicon validation (10 mos)
XPLOCC Technologies
Project Intern (1 mo)
Education
Master of Technology - MTech at Dr. B. R. Ambedkar National Institute of Technology (NIT), Jalandhar
Bachelor of Technology - BTech at SHRI RAMSWAROOP MEMORIAL COLLEGE OF ENGINEERING AND MANAGEMENT, LUCKNOW
intermediate at Jawahar Navodaya Vidyalaya - JNV
high school at Jawahar Navodaya Vidyalaya - JNV