Abhishek Srivastava

Software Engineer

Jalandhar, Punjab, India1 yr 3 mos experience

Key Highlights

  • GATE-qualified with strong VLSI Design expertise.
  • Hands-on experience with Xilinx Vivado and Cadence Virtuoso.
  • Eager to innovate in the semiconductor industry.
Stackforce AI infers this person is a VLSI Design intern with a focus on semiconductor technology and validation.

Contact

Skills

Core Skills

Static Time Analysis

Other Skills

Xilinx VivadoMATLABC (Programming Language)CMOSsystem Verilog assertionSystemVerilogPhysical design flowUnit TestingPower OptimizationClock Tree SynthesisDFTVoltageTCLApplication-Specific Integrated Circuits (ASIC)Design Flow

About

I am a Intern at Intel and a Master's student specializing in VLSI Design from NIT Jalandhar. I have Subject knowledge and technical skills in Verilog, System Verilog , System Verilog Assertion, Embedded C ,C, C++ , TCL , GitHub Physical design flow ,Static time analysis, Clock tree synthesis (CTS),PVT, Synthesis hands-on experience with tools like Xilinx VIVADO and Cadence Virtuoso. GATE-qualified During Internship I involves in creating the Unit Test coverage for uncovered and new functions and mocked the code to simulate HW conditions to meet all flows for secure device manager configuration functions. Debugging using Pre-Silicon RTL simulation bit-stream file on silicon to analysis the waveform and Debugging of faulty Firmware I am enthusiastic about contributing to innovative projects in the semiconductor industry. Eager to connect for job opportunities and discussions on advancing VLSI technology. Let's explore possibilities in the world of VLSI together! ๐ŸŒ๐Ÿ’ผ

Experience

1 yr 3 mos
Total Experience
1 yr 3 mos
Average Tenure
1 yr 3 mos
Current Experience

Analog devices

Manufacturing Engineer

Feb 2025 โ€“ Present ยท 1 yr 3 mos ยท Gandhinagar, Gujarat, India

Intel corporation

Post silicon validation

Jul 2023 โ€“ May 2024 ยท 10 mos ยท Bengaluru, Karnataka, India ยท Hybrid

static time analysisXilinx Vivado

Xplocc technologies

Project Intern

Jun 2018 โ€“ Jul 2018 ยท 1 mo ยท Lucknow, Uttar Pradesh, India ยท On-site

MATLABC (Programming Language)

Education

Dr. B. R. Ambedkar National Institute of Technology (NIT), Jalandhar

Master of Technology - MTech โ€” VLSI DESIGN

Aug 2022 โ€“ Sep 2024

SHRI RAMSWAROOP MEMORIAL COLLEGE OF ENGINEERING AND MANAGEMENT, LUCKNOW

Bachelor of Technology - BTech โ€” Electronic and Communications Engineering

Jan 2016 โ€“ Jan 2020

Jawahar Navodaya Vidyalaya - JNV

intermediate โ€” pcm

Jawahar Navodaya Vidyalaya - JNV

high school โ€” science

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