Raja Kameswari Kollipara — Software Engineer
Circuit design : Designed a circuit using cadence virtuoso and to improve the efficiency redesigned the circuit also created the Layout for some circuits and verify the DRC and LVS and simulated it VERILOG: Design RTL description for different circuits using verilog and verifyied it by providing the testbench also implemented in FPGA kit. Have knoweldge on the ASIC flow. Have Knoweldge about the STA(Static TIme Analysis). Also calculated the area,power of the netlist in the Synopsys DC Complier.
Stackforce AI infers this person is a VLSI design engineer with expertise in ASIC and circuit design.
Location: Bengaluru, Karnataka, India
Experience: 6 yrs 11 mos
Skills
- Asic Design
- Circuit Design
Career Highlights
- Expert in ASIC design and circuit simulation.
- Proficient in Verilog and FPGA implementation.
- Strong background in Static Time Analysis.
Work Experience
MediaTek
Synthesis and STA Engineer (6 yrs 11 mos)
Education
Master of Technology at Vellore Institute of Technology, Vellore
Bachelor of Technology - BTech at St. Ann's College of Engineering and Technology, Vetapalem(M), Chirala-523187,(CC-F0)
Intermediate at Narayana Junior College
