Vijay M — CEO

I am a SoC Design Verification Engineer with over 5 years of experience at Intel Corporation, specializing in Formal Verification for large-scale, high-performance SoC designs. My expertise spans across formal connectivity checks, FPV, SVA-based property verification, CSR validation, and advanced complexity-handling techniques, ensuring first-pass silicon success. 🔹 Leadership & Collaboration Led and trained a 15-member team in connectivity verification for server-class SoCs, driving comprehensive coverage and successful validation across multiple subsystems. Partnered with microarchitecture and design teams to capture specifications and validate connectivity across diverse domains. Worked cross-functionally to identify design flaws early, reducing downstream risks and improving product quality. 🔹 Technical Expertise Deep knowledge in SystemVerilog Assertions (SVA) — writing, debugging, and deploying formal properties. Extensive hands-on experience with Cadence JasperGold, using, FPV, Connectivity, Coverage, CSR, SPV, and SEC Apps for comprehensive verification. Applied count abstraction and the stop-at method to effectively handle verification complexity. Automated regressions using TCL, Python, and Perl, streamlining verification workflows. Verified critical blocks such as Serializer/Deserializer, DDR5 memory, APB protocol interfaces, PCIe error modules, and Fuse modules. Consistently leveraged JasperGold’s Connectivity, Coverage, and CSR Apps to ensure robust verification completeness. I am passionate about solving complex verification challenges, mentoring teams, and advancing formal verification methodologies to improve efficiency and quality in SoC design validation.

Stackforce AI infers this person is a Formal Verification Engineer specializing in high-performance SoC design validation.

Location: Bangalore, Karnataka, India

Experience: 7 yrs 9 mos